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Control Voltage Comparator. This circuit compares the voltage at the CONTROL PORT (represents power required at output) with PRIMARY CURRENT RAMP voltage (represents energy being stored for transfer to output). When RAMP
voltage exceeds CONTROL PORT voltage, the Control Voltage Comparator generates the CONTROL LIMIT signal to
turn the PWM off. The CONTROL PORT is biased to approximately + 1.3 volts. Whichever control signal, CC or CV, is more negative (calling for less output power) forward biases its output diode and determines the voltage at the CONTROL PORT.
As can be seen from the waveforms in Figure
Status Drivers. Inputs from the CC and CV Circuits indicate which circuit, if either, is regulating the power supply output. If neither circuit is regulating the output (load calling for more power than the power supply can deliver), logic circuits within Status Driver block determine that output is unregulated.
In GPIB units, CC and CV signals go to the microcomputer, which will take appropriate action, including lighting
20KHz Clock. This circuit contains a 320KHz crystal oscillator and dividers that produce 40KHz, 20KHz, and 1.25KHz signals. Both the 320KHz and 20KHz signals are supplied to the PWM, with the 20KHz signal controlling the repetition rate of the PWM.
The 40 KHz signal is supplied to the +5V Bias Supply Circuit to synchronize the PWM in that circuit to the main power supply PWM. The 1.25KHz output is supplied to the Time Delay Circuit for generating the time delay used to control the power supply
The 1.25KHz signal is subsequently disabled by the AC FAULT output from the Time Delay Circuit at the end of the time delay.
Pulse Width Modulator (PWM). The PWM generates the ON and OFF pulses that control the power FETs in the power mesh. ON pulses are generated at a 20KHz rate, and, as can be seen in Figure
An overtemperature ( OT ), overvoltage ( OV ), remote inhibit, AC FAULT condition or an INHIBIT signal from GPIB will initiate an OFF pulse, and will also trigger the Down Programmer to reduce output voltage to zero. These conditions will also cause PWM OFF to be sent to the TurnOn Overshoot Control Circuit.
OFF pulses can also be initiated by POWER LIMIT and by the trailing edge of the 20KHz clock signal. The 20KHz clock signal ensures that even if nothing else, such as CONTROL LIMIT or POWER LIMIT , initiates an OFF pulse, the FET duty cycle will be limited to less than 50%.
Overvoltage Protection (OVP). The OVP circuit monitors the power supply output voltage and compares it to a preset limit determined by a
CLEAR or ac power is turned off.
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