Common Commands Introduction to Programming
Agilent 8163A/B, 8164A/B & 8166A/B Mainframes, Fifth Edition 31
Common Status Information
There are three registers for the status information. Two of these are
status-re gisters a nd one is a n enable -registe rs. Thes e registe rs confo rm to
the IEEE Standard 488.2-1987. You can find further descriptions of these
registers under *ESE, *ESR?, and *STB?.
Figure2 shows how the Standard Event Status Enable Mask (SESEM)
and the Stan dard Event St atus Regis ter (SESR) de termine the Event Statu s
Bit (ESB) of the Status Byte.
Figure 2 The Event Status Bit
The SESR contains the information about events th at are not slot specific.
For details of the function of each bit of the SESR, see “Standard Event
Status Register” on page37 .
The SESEM allows you to choose the event that may affec t the ESB of the
Status Byte. If you set a bit of the SESEM to zero, the corresponding event
cannot affect the ESB. The default is for all the bits of the SESEM to be set
to 0.
The questionable and operation status systems set the Operational Status
Bit (OSB) and the Questionable Status Bit (QSB). These status systems
are described in “The Status Model” on pa ge 33 and “Status Reporting –
The STATus Subsystem” on page6 4.
01234567
*STB? returns the Status Byte Register
Status
OSB ESB QSB
*ESR? returns the Standard Event Status Register
001
01234567
Event
100000
Status
Register
01234567
Event
111111
Status
Enable
Mask
*ESE sets the Standard Event Status Enabl e Mask
&
&
&
&
&
&
&
&

OR

Byte
All bits shown as are unused
0
MAV