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AMD AMD-8151TM AGP Tunnel Data Sheet, AGP Miscellaneous Control Register, DevA, Bits

Models: 8151

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AMD-8151TMAGP Tunnel Data Sheet

24888	Rev 3.03 - July 12, 2004	AMD-8151TMAGP Tunnel Data Sheet
AGP Miscellaneous Control Register		DevA:0x40

Default: 0000 0000h		Attribute: See below.
Bits	Description

31:8	Reserved.

7Must be low. This bit is required to be low at all times; setting it high results in undefined behavior.

6 Must be low. This bit is required to be low at all times; setting it high results in undefined behavior. 5 Must be low. This bit is required to be low at all times; setting it high results in undefined behavior. 4 Must be low. This bit is required to be low at all times; setting it high results in undefined behavior.

3FWDIS: fast write disable. Read-write. 1=DevA:0xA4[FWSUP] is low. 0=DevA:0xA4[FWSUP] is high.

28XDIS: AGP 3.0 signaling mode disable. Read-write. 0=The IC drives A_MB8XDET# low to indicate support for AGP 3.0 signaling. 1=The IC does not drive A_MB8XDET low. This bit may be used in conjunction with DevB:0x3C[SBRST] to revert back to AGP 2.0 signaling. To do this, software should (1) set DevB:0x3C[SBRST] in order to reset the AGP card, (2) set 8XDIS to cause A_MB8XDET# to float high, and (3) clear DevB:0x3C[SBRST].

1TYPEDET: AGP voltage type detection. Read only. This bit reflects the state of the A_TYPEDET# pin. 0=The AGP master supports 1.5 volt signaling. 1=The AGP master requires 3.3 volt signaling and is therefore not compatible with the IC. If this bit is detected high by BIOS, an error should be signaled.

0DBIEN: dynamic bus inversion enable. Read-write. 1= A_DBI[H, L] enabled to dynamically invert the state of the A_AD signals when the IC is driving these. This only applies to AGP 3.0 transfers in the downstream direction (fast writes and read responses to AGP master requests). For PCI transfers in the downstream direction, A_DBI[H, L] are held inactive and no inversion takes place. 0=When the IC drives the A_AD lines, A_DBI[H, L] are driven low. Note: this bit is only valid when 8x transfer rates are enabled; if (1) DevA:0xA4[AGP3MD]=0 or (2) DevA:0xA4[AGP3MD]=1 and DevA:0xA8[DRATE] is not 010b, then this field is ignored and the DBI is not enabled.

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AMD specifications AMD-8151TM AGP Tunnel Data Sheet, AGP Miscellaneous Control Register, DevA, Bits, Description

Contents

1.1Device Features Data SheetFigure 1 System block diagram 24888 Rev 3.03 - July24888 Rev 3.03 - July 2004 Advanced Micro Devices, IncTable of Contents Figure 1 System block diagram List of FiguresAMD-8151TM AGP Tunnel Data Sheet Configuration spaceList of Tables AMD-8151BL C Case Temperature3Signal Descriptions 3.1Terminology 24888 Rev 3.03 - July3.2Tunnel Link Signals 24888 Rev 3.03 - July3.3AGP Signals AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet 24888 Rev 3.03 - July3.4 Test and Miscellaneous Signals 3.5 Power and Ground3.5.1Power Plane Sequencing 4Functional Operation 4.1Overview 4.2Reset And Initialization24888 Rev 3.03 - July 4.3Clocking4.4.1Link PHY 24888 Rev 3.03 - July4.4Tunnel Links 4.5AGPLink transaction 24888 Rev 3.03 - JulyAGP transaction 4.5.2Various Behaviors24888 Rev 3.03 - July Figure 2 Configuration space5.1.1Configuration Space 5Registers 5.1Register OverviewTable 4 Memory mapped address spaces Table 3 Configuration spaces5.2AGP Device Configuration Registers Table 5 Register attributesBits AGP Device Status And Command RegisterDevA DescriptionBits 24888 Rev 3.03 - JulyDevA DescriptionDevA AMD-8151TM AGP Tunnel Data SheetAGP Miscellaneous Control Register BitsDevA 24888 Rev 3.03 - JulyAGP PHY Control Register DescriptionBits AGP PHY Skew Control RegisterDevA DescriptionDevA 24888 Rev 3.03 - JulyAGP Most Recent Request Register BitsBits AGP Command Register24888 Rev 3.03 - July DescriptionDescription AGP Control RegisterBits AGP Aperture Size RegisterDescription Link Command RegisterBits GARTHI GART base address register highBits Link Configuration And Control Register24888 Rev 3.03 - July Description24888 Rev 3.03 - July DevA 0xCC 24888 Rev 3.03 - JulyLink Frequency Capability 0 Register BitsDevA 0xE8, E4, E0 24888 Rev 3.03 - JulyLink PHY Compensation Control Registers BitsClock Control Register Bits Description24888 Rev 3.03 - July 5.3AGP Bridge Configuration RegistersAGP Bridge Status And Command Register AGP Bridge Vendor And Device ID RegisterDescription DevBBits AGP Bridge Memory Base-LimitRegistersDescription 24888 Rev 3.03 - JulyBits BitsDescription AMD-8151TM AGP Tunnel Data SheetBits Bits24888 Rev 3.03 - July Table 6 Absolute maximum ratingsTable 7 Operating ranges 6Electrical Data 6.1Absolute RatingsTable 8 Current and power consumption 6.3DC Characteristics24888 Rev 3.03 - July Input low voltage 6.4AC Characteristics Table 12 AC data for clocks24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet 24888 Rev 3.03 - JulyA PCLK to transmit strobe first strobe edge 24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data SheetFigure 3 Ball designations 7Ball DesignationsSignal name AMD-8151TM AGP Tunnel Data SheetSignal name Signal nameSignal AMD-8151TM AGP Tunnel Data SheetSignal SignalFigure 4 Package mechanical drawing 8Package SpecificationAMD-8151TM AGP Tunnel Data Sheet 24888 Rev 3.03 - JulyMode 24888 Rev 3.03 - July9Test TESTNAND tree 2 output signal is STRAPL4 AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July 24888 Rev 3.03 - July 10 Appendix 10.1 Revision History RevisionRevision