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AMD 8151 AGP Device Status And Command Register, DevA, Bits, Description, REVISION. Read only

Models: 8151

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AGP Device Status And Command Register

24888 Rev 3.03 - July 12, 2004		AMD-8151TMAGP Tunnel Data Sheet
AGP Device Status And Command Register		DevA:0x04

Default: 0210 0000h		Attribute: See below.
Bits	Description

31	DPE: detected parity error. Read only. This bit is fixed in the low state.

30	SSE: signaled system error. Read; set by hardware; write 1 to clear. 1=A system error was signaled
	(both links were flooded with sync packets) as a result of a CRC error (see
	DevA:0x[C8:C4][CRCFEN, CRCERR]). Note: this bit is cleared by PWROK reset but not by
	RESET#.

29	RMA: received master abort. Read; set by hardware; write 1 to clear. 1=A request (AGP or PCI)
	sent to the host bus received a master abort (an NXA error response). Note: this bit is cleared by
	PWROK reset but not by RESET#.

28	RTA: received target abort. Read; set by hardware; write 1 to clear. 1=A request (AGP or PCI) sent
	to the host bus received a target abort (a non-NXA error response). Note: this bit is cleared by
	PWROK reset but not by RESET#.

27:21	Read only. These bits are fixed in their default state.

20	Capabilities pointer. Read only. This bit is fixed in the high state.

19:3	Read only. These bits are fixed in their default state.

2	MASEN: PCI master enable. Read-write. This bit controls no hardware in the IC.

1	MEMEN: memory enable. Read-write. 1=Enables access to the memory space specified by
	DevA:0x10. This bit controls no hardware in the IC.

0	IO enable. Read only. This bit is fixed in the low state.

AGP Device Revision and Class Code Register		DevA:0x08

Default: 0600 00??h		Attribute: See below.
Bits	Description

31:8	CLASSCODE. Read; write once. Provides the AGP bridge class code.

7:0	REVISION. Read only.

AGP Device BIST-Header-Latency-Cache Register		DevA:0x0C

Default: 0000 0000h		Attribute: Read only.
Bits	Description

31:24	BIST. These bits fixed at their default values.

23:16	HEADER. These bits fixed at their default values.

15:8	LATENCY. These bits fixed at their default values.

7:0	CACHE. These bits fixed at their default values.

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AMD 8151 AGP Device Status And Command Register, DevA, Bits, Description, AGP Device Revision and Class Code Register

Contents

Data Sheet Figure 1 System block diagram1.1Device Features 24888 Rev 3.03 - July24888 Rev 3.03 - July 2004 Advanced Micro Devices, IncTable of Contents List of Figures AMD-8151TM AGP Tunnel Data SheetFigure 1 System block diagram Configuration spaceList of Tables Case Temperature 3Signal Descriptions 3.1TerminologyAMD-8151BL C 24888 Rev 3.03 - July3.2Tunnel Link Signals 24888 Rev 3.03 - JulyAMD-8151TM AGP Tunnel Data Sheet 3.3AGP Signals24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet 24888 Rev 3.03 - July3.5 Power and Ground 3.4 Test and Miscellaneous Signals3.5.1Power Plane Sequencing 4.2Reset And Initialization 24888 Rev 3.03 - July4Functional Operation 4.1Overview 4.3Clocking24888 Rev 3.03 - July 4.4Tunnel Links4.4.1Link PHY 4.5AGP24888 Rev 3.03 - July AGP transactionLink transaction 4.5.2Various BehaviorsFigure 2 Configuration space 5.1.1Configuration Space24888 Rev 3.03 - July 5Registers 5.1Register OverviewTable 3 Configuration spaces 5.2AGP Device Configuration RegistersTable 4 Memory mapped address spaces Table 5 Register attributesAGP Device Status And Command Register DevABits Description24888 Rev 3.03 - July DevABits DescriptionAMD-8151TM AGP Tunnel Data Sheet AGP Miscellaneous Control RegisterDevA Bits24888 Rev 3.03 - July AGP PHY Control RegisterDevA DescriptionAGP PHY Skew Control Register DevABits Description24888 Rev 3.03 - July AGP Most Recent Request RegisterDevA BitsAGP Command Register 24888 Rev 3.03 - JulyBits DescriptionAGP Control Register BitsDescription AGP Aperture Size RegisterLink Command Register BitsDescription GARTHI GART base address register highLink Configuration And Control Register 24888 Rev 3.03 - JulyBits Description24888 Rev 3.03 - July 24888 Rev 3.03 - July Link Frequency Capability 0 RegisterDevA 0xCC Bits24888 Rev 3.03 - July Link PHY Compensation Control RegistersDevA 0xE8, E4, E0 BitsClock Control Register Bits Description5.3AGP Bridge Configuration Registers AGP Bridge Status And Command Register24888 Rev 3.03 - July AGP Bridge Vendor And Device ID RegisterDevB BitsDescription AGP Bridge Memory Base-LimitRegisters24888 Rev 3.03 - July BitsDescription BitsAMD-8151TM AGP Tunnel Data Sheet BitsDescription BitsTable 6 Absolute maximum ratings Table 7 Operating ranges24888 Rev 3.03 - July 6Electrical Data 6.1Absolute Ratings6.3DC Characteristics Table 8 Current and power consumption24888 Rev 3.03 - July Input low voltage Table 12 AC data for clocks 6.4AC Characteristics24888 Rev 3.03 - July 24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data SheetA PCLK to transmit strobe first strobe edge AMD-8151TM AGP Tunnel Data Sheet Figure 3 Ball designations24888 Rev 3.03 - July 7Ball DesignationsAMD-8151TM AGP Tunnel Data Sheet Signal nameSignal name Signal nameAMD-8151TM AGP Tunnel Data Sheet SignalSignal Signal8Package Specification AMD-8151TM AGP Tunnel Data SheetFigure 4 Package mechanical drawing 24888 Rev 3.03 - July24888 Rev 3.03 - July 9TestMode TESTAMD-8151TM AGP Tunnel Data Sheet NAND tree 2 output signal is STRAPL424888 Rev 3.03 - July 10 Appendix 10.1 Revision History Revision 24888 Rev 3.03 - JulyRevision