24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

In summary, Stop Grant broadcasts with SMAF fields specified by DevA:0xF0[ICGSMAF] enable the clock gating window and STPCLK deassertion broadcasts disable the window. If LDTSTOP# is asserted while the clock gating window is enabled, then clock gating occurs.

Also, DevA:0xF0[ECGSMAF] may be used in a similar way to disable A_PCLK and the internal clock grids associated with the AGP bridge. The same rules for the clock gating window that apply to DevA:0xF0[ICGS- MAF] also apply to DevA:0xF0[ECGSMAF]. If clock gating is enabled, then A_PCLK is forced low within two clock periods after LDTSTOP# is asserted. It becomes active again within two clock periods after LDT- STOP# is deasserted. It is required that there be no AGP-card-initiated upstream or downstream traffic while A_PCLK is gated. In addition, it is required that there be no host accesses to the bridge or internal registers in progress from the time that LDTSTOP# is asserted for clock gating until the link reconnects after LDTSTOP# is deasserted.

4.4Tunnel Links

HyperTransport link A supports CLK receive and transmit frequencies of 200, 400, 600, and 800 MHz. Link B supports frequencies of 200 and 400 MHz. The side A and side B frequencies are independent of each other.

4.4.1Link PHY

The PHY includes automatic compensation circuitry and a software override mechanism, as specified by DevA:0x[E8, E4, E0]. The IC only implements synchronous mode clock forwarding FIFOs. So only the link receive and transmit frequencies specified in DevA:0x[D0, CC][FREQB, FREQA] are allowed.

4.5AGP

The AGP bridge supports AGP 3.0 signaling at 8x and 4x data rates and 1.5-volt AGP 2.0 signaling at 4x, 2x, and 1x data rates. 64-bit upstream and 32-bit downstream addressing is supported. AGP 3.0 dynamic bus inver- sion is supported on output signals in 8X mode only, not in 4X mode; dynamic bus inversion on input signals is supported in both 4X and 8X modes.

4.5.1Tags, UnitIDs, And Ordering

The IC requires three HyperTransportTM technology-defined UnitIDs. They are allocated as follows:

•First UnitID is not used. This is to avoid a potential conflict with the host (because it may be zero; see DevA:0xC0[BUID]).

•Second UnitID is used for PCI-mode upstream requests and responses to host requests.

•Third UnitID is used for AGP (high priority and low priority) upstream requests.

The SrcTag value that is assigned to upstream non-posted AGP requests increments with each request from 0 to 27 and then rolls over to 0 again; the first SrcTag assigned after reset is 0. Up to 28 non-posted link requests may be outstanding at a time. The SrcTag value that is assigned to non-posted PCI requests is always 28.

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AMD 8151 specifications Tunnel Links, Link PHY, Agp, Tags, UnitIDs, And Ordering
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8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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