24888 Rev 3.03 - July 12, 2004

 

AMD-8151TMAGP Tunnel Data Sheet

 

 

 

 

 

 

 

Pin name and description

IO cell

Power

AGP 3.0

AGP 2.0

 

type

plane

Signaling

Signaling

 

 

 

 

 

 

 

 

 

 

During

After

During

After

 

 

 

reset

reset

reset

reset

 

 

 

 

 

 

 

A_GNT#. AGP master grant signal.

Output

VDD15

Term

Low

PU

High

 

 

 

 

 

 

 

A_IRDY#. AGP master ready signal.

IO

VDD15

Term

Term

PU

PU

 

 

 

 

 

 

 

A_MB8XDET#. This pin is controlled by DevA:0x40[8XDIS]. It

Output

VDD15

Low

Low

Low

Low

is designed to be connected to the AGP connector to indicate

 

 

 

 

 

 

support for AGP 3.0 signaling.

 

 

 

 

 

 

 

 

 

 

 

 

 

A_PAR. AGP parity signal.

IO

VDD15

Term

Term

PU

Low

 

 

 

 

 

 

 

A_PCLK. 66 MHz AGP clock.

Output

VDD33

Func.

Func.

Func.

Func.

 

 

 

 

 

 

 

A_PLLCLKO. PLL clock output. See section 4.3 for details.

Output

VDD33

Func.

Func.

Func.

Func.

 

 

 

 

 

 

 

A_PLLCLKI. PLL clock input. See section 4.3 for details.

Input

VDD33

 

 

 

 

 

 

 

 

 

 

 

A_REFCG. AGP signal reference output.

Analog

VDD15

 

 

 

 

 

output

 

 

 

 

 

 

 

 

 

 

 

 

A_REFGC. AGP signal reference input.

Analog

VDD15

 

 

 

 

 

input

 

 

 

 

 

 

 

 

 

 

 

 

A_REQ#. AGP master request signal.

Input

VDD15

Term

Term

PU

PU

 

 

 

 

 

 

 

A_RESET#. AGP bus reset signal. This is asserted whenever

Output

VDD33

Low

High

Low

High

RESET# is asserted or when programmed by

 

 

 

 

 

 

DevB:0x3C[SBRST]. Assertion of this pin does not reset any logic

 

 

 

 

 

 

internal to the IC.

 

 

 

 

 

 

 

 

 

 

 

 

 

A_RBF#. AGP read buffer full signal.

Input

VDD15

Term

Term

PU

PU

 

 

 

 

 

 

 

A_SBSTB_[P, N]. AGP differential side band address strobe. In

Input

VDD15

Term

Term

_P: PU

_P: PU

AGP 3.0 signaling mode, A_SBSTB_P is the first strobe and

 

 

 

 

_N: PD

_N: PD

A_SBSTB_N is the second strobe.

 

 

 

 

 

 

 

 

 

 

 

 

 

A_SBA[7:0]. AGP side band address signals.

Input

VDD15

Term

Term

PU

PU

 

 

 

 

 

 

 

A_ST[2:0]. AGP status signals.

Output

VDD15

Term

Low

PU

Low

 

 

 

 

 

 

 

A_STOP#. AGP target abort signal.

IO

VDD15

Term

Term

PU

PU

 

 

 

 

 

 

 

A_TRDY#. AGP target ready signal.

IO

VDD15

Term

Term

PU

PU

 

 

 

 

 

 

 

A_TYPEDET#. AGP IO voltage level type detect. 0=1.5 volts;

Input

VDD33

 

 

 

 

1=3.3 volts (not supported by the IC). The state of this pin is

 

 

 

 

 

 

provided in DevA:0x40[TYPEDET]. This pin is also used for test-

 

 

 

 

 

 

mode selection; see section 9. This signal requires an external

 

 

 

 

 

 

pullup resistor to VDD33 on the systemboard.

 

 

 

 

 

 

 

 

 

 

 

 

 

A_WBF#. AGP write buffer full signal.

Input

VDD15

Term

Term

PU

PU

 

 

 

 

 

 

 

The SERR# and PERR# signals are not supported on the AGP bridge.

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AMD 8151 specifications Rev 3.03 July 12, SERR# and PERR# signals are not supported on the AGP bridge

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.