AMD 8151 Rev 3.03 - July, Link PHY Compensation Control Registers, DevA 0xE8, E4, E0, Bits

Models: 8151

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Link PHY Compensation Control Registers

24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

Link PHY Compensation Control Registers

DevA:0x[E8, E4, E0]

 

 

The link PHY circuitry includes automatic compensation that is used to adjust the electrical characteristics for the link transmitters and receivers on both sides of the tunnel. There is one compensation circuit for the receiv- ers and one for each polarity of the transmitters. These registers provide visibility into the calculated output of the compensation circuits, the ability to override the calculated value with software-controlled values, and the ability to offset the calculated values with a fixed difference. The overrides and difference values may be dif- ferent between sides A and B of the tunnel. These registers specify the compensation parameters as follows:

DevA:0xE0: transmitter rising edge (P) drive strength compensation.

DevA:0xE4: transmitter falling edge (N) drive strength compensation.

DevA:0xE8: receiver impedance compensation.

For DevA:0x[E4, E0], higher values represent higher drive strength; the values range from 01h to 13h (19 steps). For DevA:0xE8, higher values represent lower impedance; the values range from 00h to 1Fh (32 steps).

Note: the default state of these registers is set by PWROK reset; assertion of RESET# does not alter any of the fields.

Default: See below.

Attribute: See below.

Bits

Description

 

 

 

31

Must be low. Read-write. This bit is required to be low at all times; setting it high results in undefined

 

behavior.

 

 

 

 

30:21

Reserved.

 

 

 

20:16

CALCCOMP: calculated compensation value. Read only. This provides the calculated value from

 

the auto compensation circuitry. The default value of this field is not predictable.

 

 

 

15

Reserved.

 

 

 

14:13

BCTL: link side B PHY control value. Read-write. These two bits combine to specify the PHY

 

compensation value that is applied to side B of the tunnel as follows:

 

BCTL

Description

 

00b

Apply CALCCOMP directly as the compensation value.

 

01b

Apply BDATA directly as the compensation value.

 

10b

Apply the sum of CALCCOMP and BDATA as the compensation value. In

 

 

DevA:0x[E4, E0], if the sum exceeds 13h, then 13h is applied. In DevA:0x[E8], if the

 

 

sum exceeds 1Fh, then 1Fh is applied.

 

11b

Apply the difference of CALCCOMP minus BDATA as the compensation value. If the

 

 

difference is less than 01h, then 01h is applied.

 

The default value of this field (from PWROK reset) is controlled by the CMPOVR signal. If

 

CMPOVR = 0, the default is 00b. If CMPOVR = 1, the default is 01b.

 

 

12:8

BDATA: link side B data value. Read-write. This value is applied to the side B of the tunnel PHY

 

compensation as described in BCTL. The default for DevA:0x[E4, E0] is 08h. The default for

 

DevA:0xE8 is 0Fh.

 

 

 

7

Reserved.

 

 

 

 

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AMD 8151 specifications Rev 3.03 - July, Link PHY Compensation Control Registers, DevA 0xE8, E4, E0, Bits, Description