AMD 8151 Rev 3.03 - July, Link Configuration And Control Register, Bits, Description

24888 Rev 3.03 - July 12, 2004 AMD-8151TMAGP Tunnel Data Sheet

26MASHST: master host. Read; set and cleared by hardware. This bit indicates which link is the path to the master (or only) host bridge on the HyperTransport™ technology chain. 1=The hardware set this bit as a result of a write command from the B side of the tunnel to any of the bytes of DevA:0xC0[31:16]. 0=The hardware cleared this bit as a result of a write command from the A side of the tunnel to any of the bytes of DevA:0xC0[31:16]. This bit, along with DEFDIR, is used to determine the side of the tunnel to which AGP master requests are sent.

25:21	UnitID count. Read only. Specifies the number of UnitIDs used by the IC (three).
20:16	BUID: base UnitID. Read-write. This specifies the link-protocol base UnitID. The IC's logic uses
	this value to determine the UnitIDs for link request and response packets. When a new value is
	written to this field, the response includes a UnitID that is based on the new value in this register.
	Note: some legacy operating systems may require that this value be set to zero for normal operation
	so that the AGP capability block is part of device 0. Since the IC does not use the base unit ID in any
	link transactions, there is no conflict with the host unit ID. However, at boot, BIOS is required to
	temporarily change the BUID value of the IC so that the BUID values in downstream devices may be
	initialized. After downstream BUID values are initialized, this field may be set to zero to be
	compatible with legacy operating systems.
15:8	Reserved.
7:0	Capabilities ID. Read only. Specifies the capabilities ID for link configuration space.
Link Configuration And Control Register		DevA:0xC4 and DevA:0xC8

DevA:0xC4 applies side A of the tunnel and DevA:0xC8 applies to side B of the tunnel. The default value for bit[5] may vary (see the definition).

Default: ??11 0020h for DevA:0xC4 and ??00 0020h for DevA:0xC8.Attribute: See below.

Bits	Description
31	Reserved.
30:28	LWO: link width out. Read-write. Specifies the operating width of the outgoing link. Legal values
	are 001b (16 bits; DevA:0xC4 only), 000b (8 bits), 101b (4 bits), 100b (2 bits), and 111b (not
	connected). Note: this field is cleared by PWROK reset but not by RESET#; the default value of this
	field depends on the widths of the links of the connecting device, per the link specification. Note:
	after this field is updated, the link width does not change until either RESET# is asserted or a link
	disconnect sequence occurs through or LDTSTOP#.
27	Reserved.
26:24	LWI: link width in. Read-write. Specifies the operating width of the incoming link. Legal values are
	001b (16 bits; DevA:0xC4 only), 000b (8 bits), 101b (4 bits), 100b (2 bits), and 111b (not connected).
	Note: this field is cleared by PWROK reset but not by RESET#; the default value of this field depends
	on the widths of the links of the connecting device, per the link specification. Note: after this field is
	updated, the link width does not change until either RESET# is asserted or a link disconnect sequence
	occurs through an LDTSTOP# assertion.
23	Reserved.
22:20	Max link width out. Read only. This specifies the width of the outgoing link to be 16 bits wide for
	side A and 8 bits wide for side B.
19	Reserved.

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