AMD 8151 specifications Appendix Revision History

24888 Rev 3.03 - July 12, 2004 AMD-8151TMAGP Tunnel Data Sheet

NAND tree 3: output signal is STRAPL[3].

1	STRAPL[1]	21	A_DBIL	41	A_CBE_L[2]	61	A_AD[12]	STRAPL[19]
2	STRAPL[8]	22	A_DBIH	42	A_CBE_L[3]	62	A_AD[13]
3	STRAPL[10]	23	A_AD[31]	43	A_ST[0]	63	A_AD[11]
4	STRAPL[9]	24	A_AD[30]	44	A_ST[1]	64	A_AD[10]
5	A_GC8XDET#	25	A_AD[29]	45	A_ST[2]	65	A_AD[9]
6	A_SBA[0]	26	A_AD[28]	46	A_MB8XDET#	66	A_AD[8]
7	A_SBA[1]	27	A_AD[27]	47	A_RBF#	67	A_ADSTB0_N
8	A_SBA[2]	28	A_AD[26]	48	A_WBF#	68	A_ADSTB0_P
9	A_SBA[3]	29	A_AD[25]	49	STRAPL[14]	69	A_CBE_L[0]
10	A_SBSTB_N	30	A_AD[24]	50	STRAPL[15]	70	A_AD[7]
11	A_SBSTB_P	31	A_ADSTB1_N	51	STRAPL[17]	71	A_AD[6]
12	A_SBA[4]	32	A_ADSTB1_P	52	STRAPL[16]	72	A_AD[5]
13	A_SBA[5]	33	A_AD[23]	53	A_IRDY#	73	A_AD[4]
14	A_SBA[6]	34	A_AD[22]	54	A_DEVSEL#	74	A_AD[3]
15	A_SBA[7]	35	A_AD[21]	55	A_FRAME#	75	A_AD[1]
16	A_GNT#	36	A_AD[20]	56	STRAPL[6]	76	A_AD[2]
17	STRAPL[11]	37	A_AD[19]	57	A_TRDY#	77	A_AD[0]
18	A_REQ#	38	A_AD[17]	58	A_CBE_L[1]	78	A_STOP#
19	STRAPL[13]	39	A_AD[18]	59	A_AD[15]	79	A_PAR
20	STRAPL[7]	40	A_AD[16]	60	A_AD[14]	80	STRAPL[18]

Nand tree 4: output signal is STRAPL[2].

1	CMPOVR	6	A_PLLCLKI	11	A_PCLK
2	RESET#	7	STRAPL[20]
3	PWROK	8	STRAPL[21]
4	REFCLK	9	STRAPL[22]
5	A_PLLCLKO	10	A_RESET#

Notes:

•LDTSTOP#, A_TYPEDET#, TEST, STRAPL[0], A_REFCG, A_REFGC, A_CALD, A_CALD#, A_CALS, and A_CALS# are not in the NAND trees.

•While in NAND-tree mode, the link and AGP input compensation is placed at a “mid-band” value.

•While in NAND-tree mode, the AGP signals operate under AGP 2.0 signaling rules.

10 Appendix

10.1 Revision History

Revision 3.02

•Initial release.

Revision 3.03

•Removed Preliminary.

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