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AMD specifications AMD-8151TM AGP Tunnel Data Sheet, Bits, Description, DevB 0x3C

Models: 8151

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DevB:0x3C

24888 Rev 3.03 - July 12, 2004		AMD-8151TMAGP Tunnel Data Sheet
DevB:0x24. Default: 0000 FFF0h		Attribute: Read-write.
Bits	Description

31:20	PMEMLIM. Prefetchable memory limit address bits[31:20]. See DevB:0x[30:1C] above.

19:16	Reserved.

15:4	PMEMBASE. Prefetchable memory base address bits[31:20]. See DevB:0x[30:1C] above.

3:0	Reserved.

DevB:0x30. Default: 0000 FFFFh		Attribute: Read-write.
Bits	Description

31:16	IOLIM. IO limit address bits[31:16]. See DevB:0x[30:1C] above.

15:0	IOBASE. IO base address bits[31:16]. See DevB:0x[30:1C] above.

AGP Bridge Interrupt and Bridge Control Register		DevB:0x3C

Default: 0000 00FFh		Attribute: See below.
Bits	Description

31:23	Reserved.

22SBRST: AGP bus reset. Read-write. 1=A_RESET# asserted; AGP bus placed into reset state. 0=A_RESET# not asserted.

21:20 Reserved.

19VGAEN: VGA decoding enable. Read-write. 1=Host-initiated commands targeting VGA- compatible address ranges are routed to the AGP bus. These include memory accesses from A0000h to BFFFFh (within the bottom megabyte of memory space only), IO accesses in which address bits[9:0] range from 3B0h to 3BBh or 3C0h to 3DFh (address bits[15:10] are not decoded, regardless of DevB:0x3C[ISAEN]; also this only applies to the first 64K of IO space; i.e., address bits[31:16] must be low). 0=The IC does not decode VGA-compatible address ranges.

18ISAEN: ISA decoding enable. Read-write. 1=The IO address window specified by DevB:0x1C[15:0] and DevB:0x30 is limited to the first 256 bytes of each 1K byte block specified; this only applies to the first 64K bytes of IO space. 0=The PCI IO window is the whole range specified by DevB:0x1C[15:0] and DevB:0x30.

17:16	Reserved.
15:8	INTERRUPT_PIN. Read; write once. These bits control no internal logic.

7:0	INTERRUPT_LINE. Read-write. These bits control no internal logic.

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AMD specifications AMD-8151TM AGP Tunnel Data Sheet, Bits, Description, DevB 0x3C

Contents

Figure 1 System block diagram Data Sheet1.1Device Features 24888 Rev 3.03 - July2004 Advanced Micro Devices, Inc 24888 Rev 3.03 - JulyTable of Contents AMD-8151TM AGP Tunnel Data Sheet List of FiguresFigure 1 System block diagram Configuration spaceList of Tables 3Signal Descriptions 3.1Terminology Case TemperatureAMD-8151BL C 24888 Rev 3.03 - July24888 Rev 3.03 - July 3.2Tunnel Link Signals3.3AGP Signals AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July 24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet3.4 Test and Miscellaneous Signals 3.5 Power and Ground3.5.1Power Plane Sequencing 24888 Rev 3.03 - July 4.2Reset And Initialization4Functional Operation 4.1Overview 4.3Clocking4.4Tunnel Links 24888 Rev 3.03 - July4.4.1Link PHY 4.5AGPAGP transaction 24888 Rev 3.03 - JulyLink transaction 4.5.2Various Behaviors5.1.1Configuration Space Figure 2 Configuration space24888 Rev 3.03 - July 5Registers 5.1Register Overview5.2AGP Device Configuration Registers Table 3 Configuration spacesTable 4 Memory mapped address spaces Table 5 Register attributesDevA AGP Device Status And Command RegisterBits DescriptionDevA 24888 Rev 3.03 - JulyBits DescriptionAGP Miscellaneous Control Register AMD-8151TM AGP Tunnel Data SheetDevA BitsAGP PHY Control Register 24888 Rev 3.03 - JulyDevA DescriptionDevA AGP PHY Skew Control RegisterBits DescriptionAGP Most Recent Request Register 24888 Rev 3.03 - JulyDevA Bits24888 Rev 3.03 - July AGP Command RegisterBits DescriptionBits AGP Control RegisterDescription AGP Aperture Size RegisterBits Link Command RegisterDescription GARTHI GART base address register high24888 Rev 3.03 - July Link Configuration And Control RegisterBits Description24888 Rev 3.03 - July Link Frequency Capability 0 Register 24888 Rev 3.03 - JulyDevA 0xCC BitsLink PHY Compensation Control Registers 24888 Rev 3.03 - JulyDevA 0xE8, E4, E0 BitsBits Description Clock Control RegisterAGP Bridge Status And Command Register 5.3AGP Bridge Configuration Registers24888 Rev 3.03 - July AGP Bridge Vendor And Device ID RegisterBits DevBDescription AGP Bridge Memory Base-LimitRegistersBits 24888 Rev 3.03 - JulyDescription BitsBits AMD-8151TM AGP Tunnel Data SheetDescription BitsTable 7 Operating ranges Table 6 Absolute maximum ratings24888 Rev 3.03 - July 6Electrical Data 6.1Absolute RatingsTable 8 Current and power consumption 6.3DC Characteristics24888 Rev 3.03 - July Input low voltage 6.4AC Characteristics Table 12 AC data for clocks24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet 24888 Rev 3.03 - JulyA PCLK to transmit strobe first strobe edge Figure 3 Ball designations AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July 7Ball DesignationsSignal name AMD-8151TM AGP Tunnel Data SheetSignal name Signal nameSignal AMD-8151TM AGP Tunnel Data SheetSignal SignalAMD-8151TM AGP Tunnel Data Sheet 8Package SpecificationFigure 4 Package mechanical drawing 24888 Rev 3.03 - July9Test 24888 Rev 3.03 - JulyMode TESTNAND tree 2 output signal is STRAPL4 AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July 24888 Rev 3.03 - July 10 Appendix 10.1 Revision History RevisionRevision