AMD 8151 Functional Operation Overview, Reset And Initialization, Clocking, Clock Gating

24888 Rev 3.03 - July 12, 2004 AMD-8151TMAGP Tunnel Data Sheet

4Functional Operation

4.1Overview

The IC connects to the host through either the side A or side B HyperTransportTM link interface. The other side of the tunnel may or may not be connected to another device. Host-initiated transactions that do not target the IC or the bridge flow through the tunnel to the downstream device. Transactions claimed by the device are passed to internal registers or to the AGP bridge.

See section 5.1 for details about the software view of the IC. See section 5.1.2 for a description of the register naming convention. See the AMD-8151TMHyperTransportTM AGP3.0 Graphics Tunnel Design Guide for addi- tional information.

4.2Reset And Initialization

RESET# and PWROK are both required to be low while the power planes to the IC are invalid and for at least 1 millisecond after the power planes are valid. Deassertion of PWROK is referred to as a cold reset. After PWROK is brought high, RESET# is required to stay low for at least 1 additional millisecond. After RESET# is brought high, the links go through the initialization sequence.

After a cold reset, the IC may be reset by asserting RESET# while PWROK remains high. This is referred to as a warm reset. RESET# must be asserted for no less than 1 millisecond during a warm reset.

4.3Clocking

It is required that REFCLK be valid in order for the IC to operate. Also, the LR[B, A]CLK inputs from the operation links must also be valid at the frequency defined DevA:0xCC[FREQA] and DevA:0xD0[FREQB]. The IC provides A_PCLK as the clock to the AGP device.

The systemboard is required to include a connection from A_PLLCLKO to A_PLLCLKI. The length of this connection is required to be approximately the same as length of the A_PCLK trace from the IC to the external AGP devices (including approximately 2.5 inches of etch on the AGP card). The IC uses this loopback to help match the external trace delay.

4.3.1Clock Gating

Internal clocks may be disabled during power-managed system states such as power-on suspend. It is required that all upstream requests initiated by the IC be suspended while in this state.

To enable clock gating, DevA:0xF0[ICGSMAF] is programmed to the values in which clock gating will be enabled. Stop Grant cycles and STPCLK deassertion link broadcasts interact to define the window in which the IC is enabled for clock gating during LDTSTOP# assertions. The system is placed into power managed states by steps that include a broadcast over the links of the Stop Grant cycle that includes the System Management Action Field (SMAF) followed by the assertion of LDTSTOP#. When the IC detects the Stop Grant broadcast which is enabled for clock gating, it enables clock gating for the next assertion of LDTSTOP#. While exiting the power-managed state, the system is required to broadcast a STPCLK deassertion message. The IC uses this message to disable clock gating during LDTSTOP# assertions. This is important because an LDTSTOP# asser- tion is not guaranteed to occur after the Stop Grant broadcast is received. The clock gating window must be closed to insure that clock gating does not occur during Stop Grant for LDTSTOP# assertions that are not asso- ciated with the power states specified by DevA:0xF0[ICGSMAF].

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