24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

 

 

18:16

Max link width in. Read only. This specifies the width of the incoming link to be 16 bits wide for

 

side A and 8 bits wide for side B.

 

 

 

 

15

Reserved.

 

14EXTCTL: extended control time during initialization. Read-write. This specifies the time in which LT[B, A]CTL is held asserted during the initialization sequence that follows an LDTSTOP# deassertion, after LR[B, A]CTL is detected asserted. 0=At least 16 bit times. 1=About 50 microseconds. Note: this bit is cleared by PWROK reset but not by RESET#.

13LDT3SEN: link three-state enable. Read-write. 1=During the LDTSTOP# disconnect sequence, the link transmitter signals are placed into the high impedance state and the receivers are prepared for the high impedance mode. For the receivers, this includes cutting power to the receiver differential amplifiers and ensuring that there are no resultant high-current paths in the circuits. 0=During the LDTSTOP# disconnect sequence, the link transmitter signals are driven, but in an undefined state, and the link receiver signals are assumed to be driven. Note: this bit is cleared by PWROK reset but not by RESET#. AMD recommends that this bit be set high in single-processor systems and be low in multi-processor systems.

12:10

Reserved.

9:8

CRCERR: CRC Error. Read; set by hardware; write 1 to clear. Bit[9] applies to the upper byte of

 

the link (DevA:0xC4 only) and bit[8] applies to the lower byte. 1=The hardware detected a CRC error

 

on the incoming link. Note: this bit is cleared by PWROK reset but not by RESET#.

7TXOFF: transmitter off. Read; write 1 only. 1=No output signals on the link toggle; the input link receivers are disabled and the pins may float.

6ENDOCH: end of chain. Read; write 1 only or set by hardware. 1=The link is not part of the logical HyperTransport technology chain; packets which are issued or forwarded to this link are either dropped or result in an NXA error response, as appropriate; packets received from this link are ignored and CRC is not checked; if the transmitter is still enabled (TXOFF), then it drives only NOP packets with good CRC. ENDOCH may be set by writing a 1 to it or it may be set by hardware if the link is determined to be disconnected at the rising edge of RESET#.

5INITCPLT: initialization complete. Read only. This bit is set by hardware when low-level link initialization has successfully completed. If there is no device on the other end of the link, or if the device on the other side of the link is unable to properly perform link initialization, then the bit is not set. This bit is cleared when RESET# is asserted or after the link disconnect sequence completes after the assertion of LDTSTOP#.

4LKFAIL: link failure. Read; set by hardware; write 1 to clear. This bit is set high by the hardware when a CRC error is detected on the link (if enabled by CRCFEN) or if the link is not used in the system. Note: this bit is cleared by PWROK reset, not by RESET#.

3CRCERRCMD: CRC error command. Read-write. 1=The link transmission logic generates erroneous CRC values. 0=Transmitted CRC values match the values calculated per the link specification. This bit is intended to be used to check the CRC failure detection logic of the device on the other side of the link.

2Reserved.

1CRCFEN: CRC flood enable. Read-write. 1=CRC errors (in link A for DevA:0xC4[CRCFEN]; in link B for DevA:0xC8[CRCFEN]) result in sync packets to both outgoing links, DevA:0x04[SSE] is set, and the LKFAIL bit is set. 0=CRC errors do not result in sync packets, setting of DevA:0x04[SSE] or the LKFAIL bit.

0Reserved.

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AMD 8151 specifications Rev 3.03 July 12
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8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.
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