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AMD 8151 specifications AGP Control Register, Bits, Description, AGP Aperture Size Register

Models: 8151

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AGP Control Register

24888 Rev 3.03 - July 12, 2004AMD-8151TMAGP Tunnel Data Sheet

2:0	DRATE: data transfer mode rate. This field is combined with DevA:0xA4[AGP3MD] to specify
	the AGP data rate as follows:
	AGP3MD	DRATE
	X	000	No AGP mode selected.
	0	001	1x AGP rate; AGP 2.0 signaling.
	0	010	2x AGP rate; AGP 2.0 signaling.
	0	100	4x AGP rate; AGP 2.0 signaling.
	1	001	4x AGP rate; AGP 3.0 signaling.
	1	010	8x AGP rate; AGP 3.0 signaling.
	1	100	Reserved.

AGP Control Register			DevA:0xB0

Default: 0000 0000h			Attribute: Read-write.
Bits	Description

31:10	Reserved.

9CALDIS: calibration cycle disable. 1=Calibration cycles (as defined in DevA:0xA8[PCALCYC]) are disabled.

8APEREN: graphics aperture enable. This bit controls no hardware in the IC. It is expected that the state of this bit is copied into the host by software.

7GTLBEN: graphics translation look-aside buffer enable. This bit controls no hardware in the IC. It is expected that the state of this bit is copied into the host by software.

6:0	Reserved.
AGP Aperture Size Register		DevA:0xB4

Default: 0001 0F00h		Attribute: See below.
Bits	Description

31:28 PGSZSEL: page size select. Read-write. The only legal value for these bits is 0000b, which specifies

a4-kilobyte page.

27 Reserved.

26:16 Page size support. Read only. These bits are fixed in their default state to indicate that the IC supports 4-kilobyte pages.

15:12 Reserved.

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AMD 8151 specifications AGP Control Register, Bits, Description, AGP Aperture Size Register

Contents

24888 Rev 3.03 - July Data SheetFigure 1 System block diagram 1.1Device Features2004 Advanced Micro Devices, Inc 24888 Rev 3.03 - JulyTable of Contents Configuration space List of FiguresAMD-8151TM AGP Tunnel Data Sheet Figure 1 System block diagramList of Tables 24888 Rev 3.03 - July Case Temperature3Signal Descriptions 3.1Terminology AMD-8151BL C24888 Rev 3.03 - July 3.2Tunnel Link Signals24888 Rev 3.03 - July 3.3AGP SignalsAMD-8151TM AGP Tunnel Data Sheet 24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet3.5.1Power Plane Sequencing 3.4 Test and Miscellaneous Signals3.5 Power and Ground 4.3Clocking 4.2Reset And Initialization24888 Rev 3.03 - July 4Functional Operation 4.1Overview4.5AGP 24888 Rev 3.03 - July4.4Tunnel Links 4.4.1Link PHY4.5.2Various Behaviors 24888 Rev 3.03 - JulyAGP transaction Link transaction5Registers 5.1Register Overview Figure 2 Configuration space5.1.1Configuration Space 24888 Rev 3.03 - JulyTable 5 Register attributes Table 3 Configuration spaces5.2AGP Device Configuration Registers Table 4 Memory mapped address spacesDescription AGP Device Status And Command RegisterDevA BitsDescription 24888 Rev 3.03 - JulyDevA BitsBits AMD-8151TM AGP Tunnel Data SheetAGP Miscellaneous Control Register DevADescription 24888 Rev 3.03 - JulyAGP PHY Control Register DevADescription AGP PHY Skew Control RegisterDevA BitsBits 24888 Rev 3.03 - JulyAGP Most Recent Request Register DevADescription AGP Command Register24888 Rev 3.03 - July BitsAGP Aperture Size Register AGP Control RegisterBits DescriptionGARTHI GART base address register high Link Command RegisterBits DescriptionDescription Link Configuration And Control Register24888 Rev 3.03 - July Bits24888 Rev 3.03 - July Bits 24888 Rev 3.03 - JulyLink Frequency Capability 0 Register DevA 0xCCBits 24888 Rev 3.03 - JulyLink PHY Compensation Control Registers DevA 0xE8, E4, E0Bits Description Clock Control RegisterAGP Bridge Vendor And Device ID Register 5.3AGP Bridge Configuration RegistersAGP Bridge Status And Command Register 24888 Rev 3.03 - JulyAGP Bridge Memory Base-LimitRegisters DevBBits DescriptionBits 24888 Rev 3.03 - JulyBits DescriptionBits AMD-8151TM AGP Tunnel Data SheetBits Description6Electrical Data 6.1Absolute Ratings Table 6 Absolute maximum ratingsTable 7 Operating ranges 24888 Rev 3.03 - July24888 Rev 3.03 - July Table 8 Current and power consumption6.3DC Characteristics Input low voltage 24888 Rev 3.03 - July 6.4AC CharacteristicsTable 12 AC data for clocks A PCLK to transmit strobe first strobe edge AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July 7Ball Designations AMD-8151TM AGP Tunnel Data SheetFigure 3 Ball designations 24888 Rev 3.03 - JulySignal name AMD-8151TM AGP Tunnel Data SheetSignal name Signal nameSignal AMD-8151TM AGP Tunnel Data SheetSignal Signal24888 Rev 3.03 - July 8Package SpecificationAMD-8151TM AGP Tunnel Data Sheet Figure 4 Package mechanical drawingTEST 24888 Rev 3.03 - July9Test Mode24888 Rev 3.03 - July NAND tree 2 output signal is STRAPL4AMD-8151TM AGP Tunnel Data Sheet Revision 24888 Rev 3.03 - July10 Appendix 10.1 Revision History Revision