Manuals / AMD / Home Audio / Speaker

AMD 8151 specifications Rev 3.03 - July, AGP Most Recent Request Register, DevA, Bits, Description

Models: 8151

1 45

Download 45 pages 54.77 Kb

Page 21

24888 Rev 3.03 - July 12, 2004	AMD-8151TMAGP Tunnel Data Sheet
AGP Most Recent Request Register	DevA:0x60

As each PIPE mode or SBA mode AGP request is transferred into the IC, the fields are placed into this register. Thus, this register provides the fields of the most recent AGP requests. Any sticky bits from prior requests that have not been updated in the current request are also valid. Note: fences are not captured by this register.

Default: 0000 0000 0000 0000h		Attribute: Read only.
Bits	Description

63:44	Reserved.

43:40	MRC: most recent command field. Specifies the command field of the most recent AGP request.
	0h=LP (low priority) read. 1h=HP (high priority) read. 4h=LP write. 5h=HP write. 8h=LP long read.
	9h=HP long read. Ah=Flush.

39:3	MRA: most recent address. Specifies address bits[39:3] of the most recent AGP request.

2:0	MRL: most recent length field. Specifies the length field of the most recent AGP request.

AGP Revision and Capability Register		DevA:0xA0

Default: 0030 C002h		Attribute: Read only.
Bits	Description

31:24	Reserved.

23:16	AGP specification. This field is hardwired to indicate that the IC conforms to AGP specification
	revision 3.

15:8	Next capabilities block. Specifies the offset to the next capabilities block.

7:0	Capabilities type. Specifies the AGP capabilities block.

AGP Status Register		DevA:0xA4

Default: 1F00 0B2?h (see bit descriptions for bits[3:0])Attribute: Read only.

Bits	Description

31:24	RQ: maximum number of outstanding requests. This field is set to indicate support for 32
	outstanding requests.

23:18	Reserved.

17	Isochronous support. This bit fixed in the low state to indicate that the IC does not support
	isochronous modes.

16:13	Reserved.

12:10	Calibration cycle. This field is set to indicate a requirement for calibration cycles every 64 millisec-
	onds.

9	SBA support. This field is set to indicate support for SBA.

8	Coherency. This bit fixed high.

7	64-bit GART support. This bit fixed low.

6	Host translation#. This bit fixed low.

5	Greater-than 4 gigabyte support. This bit fixed high.


	21

Image 21

AMD 8151 Rev 3.03 - July, AGP Most Recent Request Register, DevA, Bits, Description, AGP Revision and Capability Register

Contents

Figure 1 System block diagram Data Sheet1.1Device Features 24888 Rev 3.03 - July2004 Advanced Micro Devices, Inc 24888 Rev 3.03 - JulyTable of Contents AMD-8151TM AGP Tunnel Data Sheet List of FiguresFigure 1 System block diagram Configuration spaceList of Tables AMD-8151BL C 3Signal Descriptions 3.1Terminology24888 Rev 3.03 - July 2Ordering Information24888 Rev 3.03 - July 3.2Tunnel Link Signals3.3AGP Signals AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July 24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet3.4 Test and Miscellaneous Signals 3.5 Power and Ground3.5.1Power Plane Sequencing 24888 Rev 3.03 - July 4.2Reset And Initialization4Functional Operation 4.1Overview 4.3Clocking4.4Tunnel Links 24888 Rev 3.03 - July4.4.1Link PHY 4.5AGPAGP transaction 24888 Rev 3.03 - JulyLink transaction 4.5.2Various Behaviors5.1.1Configuration Space Figure 2 Configuration space24888 Rev 3.03 - July 5Registers 5.1Register Overview5.2AGP Device Configuration Registers Table 3 Configuration spacesTable 4 Memory mapped address spaces Table 5 Register attributesDevA AGP Device Status And Command RegisterBits DescriptionDevA 24888 Rev 3.03 - JulyBits DescriptionAGP Miscellaneous Control Register AMD-8151TM AGP Tunnel Data SheetDevA BitsAGP PHY Control Register 24888 Rev 3.03 - JulyDevA DescriptionDevA AGP PHY Skew Control RegisterBits DescriptionAGP Most Recent Request Register 24888 Rev 3.03 - JulyDevA Bits24888 Rev 3.03 - July AGP Command RegisterBits DescriptionBits AGP Control RegisterDescription AGP Aperture Size RegisterBits Link Command RegisterDescription GARTHI GART base address register high24888 Rev 3.03 - July Link Configuration And Control RegisterBits Description24888 Rev 3.03 - July Link Frequency Capability 0 Register 24888 Rev 3.03 - JulyDevA 0xCC BitsLink PHY Compensation Control Registers 24888 Rev 3.03 - JulyDevA 0xE8, E4, E0 BitsBits Description Clock Control RegisterAGP Bridge Status And Command Register 5.3AGP Bridge Configuration Registers24888 Rev 3.03 - July AGP Bridge Vendor And Device ID RegisterBits DevBDescription AGP Bridge Memory Base-LimitRegistersBits 24888 Rev 3.03 - JulyDescription BitsBits AMD-8151TM AGP Tunnel Data SheetDescription BitsTable 7 Operating ranges Table 6 Absolute maximum ratings24888 Rev 3.03 - July 6Electrical Data 6.1Absolute RatingsTable 8 Current and power consumption 6.3DC Characteristics24888 Rev 3.03 - July Input low voltage 6.4AC Characteristics Table 12 AC data for clocks24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet 24888 Rev 3.03 - JulyA PCLK to transmit strobe first strobe edge Figure 3 Ball designations AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July 7Ball DesignationsSignal name AMD-8151TM AGP Tunnel Data SheetSignal name Signal nameSignal AMD-8151TM AGP Tunnel Data SheetSignal SignalAMD-8151TM AGP Tunnel Data Sheet 8Package SpecificationFigure 4 Package mechanical drawing 24888 Rev 3.03 - July9Test 24888 Rev 3.03 - JulyMode TESTNAND tree 2 output signal is STRAPL4 AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July 24888 Rev 3.03 - July 10 Appendix 10.1 Revision History RevisionRevision