24888 Rev 3.03 - July 12, 2004 |
3.3AGP Signals
In the table below, “Term” indicates the standard AGP 3.0 termination impedance to ground; “PU” indicates a weak pullup resistor; “PD” indicates a weak pulldown resistor.
Pin name and description |
| IO cell | Power | AGP 3.0 | AGP 2.0 | |||
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| type | plane | Signaling | Signaling | ||
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| During | After | During | After |
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| reset | reset | reset | reset |
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A_ADSTB0_[P, N]. AGP differential strobe for A_AD[15:0] and | IO | VDD15 | Term | Term | _P: PU | _P: PU | ||
A_CBE_L[1:0]. When AGP 3.0 signaling is enabled, |
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| _N: PD | _N: PD | ||
A_ADSTB0_P is the first strobe and A_ADSTB0_N is the second |
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strobe. |
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A_ADSTB1_[P, N]. AGP differential strobe for AD[31:16], | IO | VDD15 | Term | Term | _P: PU | _P: PU | ||
A_CBE_L[3:2], and A_DBI[H,L]. When AGP 3.0 signaling is |
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| _N: PD | _N: PD | ||
enabled, A_ADSTB1_P is the first strobe and A_ADSTB1_N is |
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the second strobe. |
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A_AD[31:0]. AGP |
| IO | VDD15 | Term | Term | PU | Low | |
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A_CBE_L[3:0]. AGP | IO | VDD15 | Term | Term | PU | Low | ||
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A_CAL[D, S] and A_CAL[D, S]#. Compensation pins for | Analog | VDD15 |
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matching impedance of system board AGP traces. See |
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DevA:0x[54, 50] for more information. These are designed to be |
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connected through resistors as follows: |
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Signal | Compensation Function | External Connection |
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A_CALD | Rising edge of data signals | Resistor to VSS |
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A_CALD# | Falling edge of data signals | Resistor to VDD15 |
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A_CALS | Rising edge of strobe signals | Resistor to VSS |
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A_CALS# | Falling edge of strobe signals | Resistor to VDD15 |
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These resistors are used by the compensation circuit. The output of |
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this circuit is combined with DevA:0x[54, 50] to determine com- |
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pensation values that are passed to the link PHYs. |
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A_DBI[H, L]. Data bus inversion [high, low]. When | IO | VDD15 | Term | Term | PU | PU | ||
DevA:0xA4[AGP3MD]=1, A_DBIL applies to AD[15:0]; |
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A_DBIH applies to AD[31:16]. 1=AD signals are inverted. |
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0=A_AD signals are not inverted. The IC uses these signals in |
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determining the polarity of the A_AD signals when they are |
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inputs. These may also be enabled to support the DBI function of |
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the IC output signals by DevA:0x40[DBIEN]. Both A_DBIH and |
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A_DBIL are strobed with A_ADSTB1_[P, N]. |
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When DevA:0xA4[AGP3MD]=0: A_DBIL is pulled low with the |
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AGP termination value and not used by the IC; A_DBIH is pulled |
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up to VDD15 through a weak resistor and becomes the AGP 2.0 |
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PIPE# input signal. |
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A_DEVSEL#. AGP device select. |
| IO | VDD15 | Term | Term | PU | PU | |
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A_FRAME#. AGP frame signal. |
| IO | VDD15 | Term | Term | PU | PU | |
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A_GC8XDET#. 0=Specifies that the graphics device supports | Input | VDD15 | PU | PU | PU | PU | ||
AGP 3.0 signaling. The state of this signal is latched on the rising | w/PU |
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edge of A_RESET# before being passed to internal logic. |
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| 8 |
