AMD 8151 Bits, Description, GARTHI GART base address register high, Link Command Register

Models: 8151

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GARTHI: GART base address register high.

24888 Rev 3.03 - July 12, 2004AMD-8151TMAGP Tunnel Data Sheet

11:0

APSIZE: graphic virtual memory aperture size. Read-write (except bits[11, 7:6, and 2:0] which

 

are read only, fixed at the default value). This field specifies the size of the aperture pointed to by

 

DevA:0x10. This field also controls read only versus read-write control over several bits in

 

DevA:0x10. It is encoded as follows:

 

 

 

 

 

 

 

 

 

 

 

DevA:0x10

DevA:0x10

 

Bits[10,

9,

8, 5,

4,

3]

Aperture size

read-write bits

read-only bits

 

1

1

1

1

1

1

32 MB

[63:25]

[24:0]

 

1

1

1

1

1

0

64 MB

[63:26]

[25:0]

 

1

1

1

1

0

0

128 MB

[63:27]

[26:0]

 

1

1

1

0

0

0

256 MB

[63:28]

[27:0]

 

1

1

0

0

0

0

512 MB

[63:29]

[28:0]

 

1

0

0

0

0

0

1024 MB

[63:30]

[29:0]

 

0

0

0

0

0

0

2048 MB

[63:31]

[30:0]

 

It is expected that the state of this field is copied into the host by software. Note: DevA:0x10[2] is

 

“read; write once,” even though it is shown as read-only above. Also, based on the state of

 

DevA:0x10[2], DevA:0x10[63:32] may be read-only, all zeros.

 

 

 

 

 

 

 

 

 

 

AGP Device GART Pointer

 

 

 

 

 

 

DevA:0xB8

 

 

 

 

 

 

 

 

 

 

This register controls no hardware in the IC. It is expected that the state of this register is copied into the host by software.

Default: 0000 0000 0000 0000h

Attribute: Read-write.

Bits

Description

 

 

 

63:32

GARTHI: GART base address register high.

 

 

31:12

GARTLO: GART base address register low.

 

 

 

11:0

Reserved.

 

 

 

 

Link Command Register

DevA:0xC0

 

 

 

Default: 0060 0008h

Attribute: See below.

Bits

Description

 

 

 

 

31:29

Slave/primary interface type. Read only.

 

28DOUI: drop on uninitialized link. Read-write. This specifies the behavior of transactions that are sent to uninitialized links. 0=Transactions that are received by the IC and forwarded to a side of the tunnel, when DevA:0x[C4/C8][INITCPLT and ENDOCH] for that side of the tunnel are both low, remain in buffers awaiting transmission indefinitely (waiting for INITCPLT to be set high). 1=Trans- actions that are received by the IC and forwarded to a side of the tunnel, when DevA:0x[C4/C8][INITCPLT and ENDOCH] for that side of the tunnel are both low, behave as if ENDOCH were high. Note: this bit is cleared by PWROK reset but not by RESET#.

27DEFDIR: default direction. Read-write. 0=Send AGP master requests to the master link host as specified by DevA:0xC0[MASHST]. 1=Send AGP master requests to the opposite side of the tunnel.

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AMD 8151 specifications Bits, Description, GARTHI GART base address register high, GARTLO GART base address register low