Garthi Gart base address register high

24888 Rev 3.03 - July 12, 2004AMD-8151TMAGP Tunnel Data Sheet

11:0	APSIZE: graphic virtual memory aperture size. Read-write (except bits[11, 7:6, and 2:0] which
	are read only, fixed at the default value). This field specifies the size of the aperture pointed to by
	DevA:0x10. This field also controls read only versus read-write control over several bits in
	DevA:0x10. It is encoded as follows:
								DevA:0x10	DevA:0x10
	Bits[10,	9,	8, 5,		4,	3]	Aperture size	read-write bits	read-only bits
	1	1	1	1	1	1	32 MB	[63:25]	[24:0]
	1	1	1	1	1	0	64 MB	[63:26]	[25:0]
	1	1	1	1	0	0	128 MB	[63:27]	[26:0]
	1	1	1	0	0	0	256 MB	[63:28]	[27:0]
	1	1	0	0	0	0	512 MB	[63:29]	[28:0]
	1	0	0	0	0	0	1024 MB	[63:30]	[29:0]
	0	0	0	0	0	0	2048 MB	[63:31]	[30:0]
	It is expected that the state of this field is copied into the host by software. Note: DevA:0x10[2] is
	“read; write once,” even though it is shown as read-only above. Also, based on the state of
	DevA:0x10[2], DevA:0x10[63:32] may be read-only, all zeros.

AGP Device GART Pointer									DevA:0xB8

This register controls no hardware in the IC. It is expected that the state of this register is copied into the host by software.

Default: 0000 0000 0000 0000h		Attribute: Read-write.
Bits	Description

63:32	GARTHI: GART base address register high.

31:12	GARTLO: GART base address register low.

11:0	Reserved.

Link Command Register		DevA:0xC0

Default: 0060 0008h		Attribute: See below.
Bits	Description

31:29	Slave/primary interface type. Read only.

28DOUI: drop on uninitialized link. Read-write. This specifies the behavior of transactions that are sent to uninitialized links. 0=Transactions that are received by the IC and forwarded to a side of the tunnel, when DevA:0x[C4/C8][INITCPLT and ENDOCH] for that side of the tunnel are both low, remain in buffers awaiting transmission indefinitely (waiting for INITCPLT to be set high). 1=Trans- actions that are received by the IC and forwarded to a side of the tunnel, when DevA:0x[C4/C8][INITCPLT and ENDOCH] for that side of the tunnel are both low, behave as if ENDOCH were high. Note: this bit is cleared by PWROK reset but not by RESET#.

27DEFDIR: default direction. Read-write. 0=Send AGP master requests to the master link host as specified by DevA:0xC0[MASHST]. 1=Send AGP master requests to the opposite side of the tunnel.

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.

AMD 8151 Garthi Gart base address register high, Gartlo Gart base address register low

Models: 8151

GARTHI: GART base address register high.

GARTLO: GART base address register low.

Link Command Register

Slave/primary interface type. Read only.

8151 specifications