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AMD 8151 Rev 3.03 - July, Link Frequency Capability 0 Register, DevA 0xCC, Bits, Description

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Link Frequency Capability 0 Register

24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

Link Frequency Capability 0 Register		DevA:0xCC
Default: 0035 0022h.		Attribute: See below.
Bits	Description

31:16	FREQCAPA: link A frequency capability. Read only. These bits indicate that A side of the tunnel
	supports 200, 400, 600, and 800 MHz link frequencies.

15:12	Reserved.

11:8	FREQA: link A frequency. Read-write. Specifies the link side A frequency. Legal values are 0h (200
	MHz), 2h (400 MHz), 4h (600 MHz), and 5h (800 MHz). Note: this bit is cleared by PWROK reset,
	not by RESET#. Note: after this field is updated, the link frequency does not change until either
	RESET# is asserted or a link disconnect sequence occurs through LDTSTOP#.

7:0	REVISION. Read only. Revision A of the IC is designed to version 1.02 of the link specification.

Link Frequency Capability 1 Register		DevA:0xD0

Default: 0035 0002h.		Attribute: See below.
Bits	Description

31:16	FREQCAPB: link B frequency capability. Read only. These bits indicate that that B side of the
	tunnel supports 200, 400, 600, and 800 MHz link frequencies.

15:12	Reserved.

11:8	FREQB: link B frequency. Read-write. Specifies the link side B frequency. Legal values are 0h (200
	MHz), and 2h (400 MHz), 4h (600 MHz), and 5h (800 MHz). Note: although it is possible to program
	this field for higher frequencies, the B link of the IC is only designed to support 200 and 400 MHz
	operation. Note: this bit is cleared by PWROK reset, not by RESET#. Note: after this field is updated,
	the link frequency does not change until either RESET# is asserted or a link disconnect sequence
	occurs through LDTSTOP#.

7:0	Link device feature capability indicator. Read only. These bits are set to indicate that the IC
	supports LDTSTOP#.

Link Enumeration Scratchpad Register		DevA:0xD4

Default: 0000 0000h.		Attribute: See below.
Bits	Description

31:16	Reserved.

15:0	ESP: enumeration scratchpad. Read-write. This field controls no hardware within the IC. Note: this
	bit is cleared by PWROK reset, not by RESET#.

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AMD 8151 Rev 3.03 - July, Link Frequency Capability 0 Register, DevA 0xCC, Bits, Description, DevA 0xD0, DevA 0xD4

Contents

24888 Rev 3.03 - July Data SheetFigure 1 System block diagram 1.1Device Features2004 Advanced Micro Devices, Inc 24888 Rev 3.03 - JulyTable of Contents Configuration space List of FiguresAMD-8151TM AGP Tunnel Data Sheet Figure 1 System block diagramList of Tables 24888 Rev 3.03 - July Case Temperature3Signal Descriptions 3.1Terminology AMD-8151BL C24888 Rev 3.03 - July 3.2Tunnel Link Signals3.3AGP Signals AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July 24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet3.4 Test and Miscellaneous Signals 3.5 Power and Ground3.5.1Power Plane Sequencing 4.3Clocking 4.2Reset And Initialization24888 Rev 3.03 - July 4Functional Operation 4.1Overview4.5AGP 24888 Rev 3.03 - July4.4Tunnel Links 4.4.1Link PHY4.5.2Various Behaviors 24888 Rev 3.03 - JulyAGP transaction Link transaction5Registers 5.1Register Overview Figure 2 Configuration space5.1.1Configuration Space 24888 Rev 3.03 - JulyTable 5 Register attributes Table 3 Configuration spaces5.2AGP Device Configuration Registers Table 4 Memory mapped address spacesDescription AGP Device Status And Command RegisterDevA BitsDescription 24888 Rev 3.03 - JulyDevA BitsBits AMD-8151TM AGP Tunnel Data SheetAGP Miscellaneous Control Register DevADescription 24888 Rev 3.03 - JulyAGP PHY Control Register DevADescription AGP PHY Skew Control RegisterDevA BitsBits 24888 Rev 3.03 - JulyAGP Most Recent Request Register DevADescription AGP Command Register24888 Rev 3.03 - July BitsAGP Aperture Size Register AGP Control RegisterBits DescriptionGARTHI GART base address register high Link Command RegisterBits DescriptionDescription Link Configuration And Control Register24888 Rev 3.03 - July Bits24888 Rev 3.03 - July Bits 24888 Rev 3.03 - JulyLink Frequency Capability 0 Register DevA 0xCCBits 24888 Rev 3.03 - JulyLink PHY Compensation Control Registers DevA 0xE8, E4, E0Bits Description Clock Control RegisterAGP Bridge Vendor And Device ID Register 5.3AGP Bridge Configuration RegistersAGP Bridge Status And Command Register 24888 Rev 3.03 - JulyAGP Bridge Memory Base-LimitRegisters DevBBits DescriptionBits 24888 Rev 3.03 - JulyBits DescriptionBits AMD-8151TM AGP Tunnel Data SheetBits Description6Electrical Data 6.1Absolute Ratings Table 6 Absolute maximum ratingsTable 7 Operating ranges 24888 Rev 3.03 - JulyTable 8 Current and power consumption 6.3DC Characteristics24888 Rev 3.03 - July Input low voltage 6.4AC Characteristics Table 12 AC data for clocks24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet 24888 Rev 3.03 - JulyA PCLK to transmit strobe first strobe edge 7Ball Designations AMD-8151TM AGP Tunnel Data SheetFigure 3 Ball designations 24888 Rev 3.03 - JulySignal name AMD-8151TM AGP Tunnel Data SheetSignal name Signal nameSignal AMD-8151TM AGP Tunnel Data SheetSignal Signal24888 Rev 3.03 - July 8Package SpecificationAMD-8151TM AGP Tunnel Data Sheet Figure 4 Package mechanical drawingTEST 24888 Rev 3.03 - July9Test ModeNAND tree 2 output signal is STRAPL4 AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July 24888 Rev 3.03 - July 10 Appendix 10.1 Revision History RevisionRevision