AMD 8151 specifications Rev 3.03 - July, AGP Command Register, Bits, Description

24888 Rev 3.03 - July 12, 2004 AMD-8151TMAGP Tunnel Data Sheet

4FWSUP: fast write support flag. 0=Fast writes are not supported. 1=Fast writes are supported. The state of this bit is controlled by DevA:0x40[FWDIS].

3AGP3MD: AGP 3.0 signaling mode detected. 1=The IC detected connection to an AGP 3.0-capable master and is programmed for AGP 3.0 signaling. 0=The IC detected connection to an AGP 2.0 or earlier capable master or is not programmed for 1.5-volt, AGP 2.0 signaling. If DevA:0x40[8XDIS]=0 and the pin A_GC8XDET#=0, then this bit is high. Otherwise, it is low.

2:0	RATE: data rate. When AGP3MD=1, then this field defaults to 011b to indicate support for 4x and
	8x data rates. When AGP3MD=0, this field defaults to 111b to indicate support for 4x, 2x, and 1x data
	rates.
AGP Command Register		DevA:0xA8
Default: 0000 0000h		Attribute: Read-write.
Bits	Description
31:13	Reserved.
12:10	PCALCYC: periodic calibration cycle. Specifies the period between calibration cycles as follows:
	000b=4 milliseconds; 001b=16 milliseconds; 010=64 milliseconds; 011b=256 milliseconds; all other
	values are reserved. When DevA:0xA4[AGP3MD]=1, calibration cycles are as specified in the AGP
	3.0 specification. When DevA:0xA4[AGP3MD]=0, calibration cycles consist of (1) the internal
	calibration logic requests the bus; (2) once granted, the calibration values are update in less than 6
	A_PCLK cycles while the AGP bus is in a quiescent state. Note: after changing this value, the IC may
	not perform another calibration cycle until the internal counter rolls over as much as 256
	microseconds later; in order to avoid this, DevA:0xB0[CALDIS] should be set high before changing
	PCALCYC and then DevA:0xB0[CALDIS] should be cleared afterward.

9SBA_EN: side band address enable. 1=SBA addressing is enabled. Note: when DevA:0xA4[AGP3MD]=1, SBA addressing is enabled and the state of this bit is ignored.

8AGPEN: AGP operation enable. 1=The IC accepts master-initiated AGP commands. 0=AGP commands are ignored.

7:6 Reserved.

5R4GEN: receive greater-than 4-gigabyte access enable. 1=The IC accepts AGP accesses to addresses greater than 4 gigabytes.

4FWEN: fast write enable. 1=Fast writes are enabled. When DevA:0xA4[FWSUP]=0, this bit is required to be programmed low; if, in this case, this bit is programmed high, then undefined behavior results.

3Reserved.

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