AMD 8151 Translation from AGP requests to link requests, AGP transaction Link transaction

24888 Rev 3.03 - July 12, 2004 AMD-8151TMAGP Tunnel Data Sheet

All AGP transactions are compliant to AGP ordering rules. APG transactions are translated into link transac- tions as follows:

AGP transaction	Link transaction
High priority write	WrSized, posted channel, PassPW = 1
High priority read	RdSized, PassPW = 1, response PassPW = 1
Low priority write	WrSized, posted channel, PassPW = 0
Low priority read	RdSized, PassPW = 0, response PassPW = 1
Low priority flush	Flush, PassPW = 0
Low priority fence	None (wait for all outstanding read responses)

Table 2: Translation from AGP requests to link requests.

4.5.2Various Behaviors

•The AGP bridge does not claim link special cycles. However, special cycles that are encoded in configura- tion cycles to device 31 of the AGP secondary bus number (per the PCI-to-PCI bridge specification) are translated to AGP bus special cycles.

•AGP and PCI read transactions that receive NXA responses from the host complete onto the AGP bus with the data provided by the host (which is required to be all 1’s, per the link specification).

•In the translation from type 1 link configuration cycles to secondary bus type 0 configuration cycles, the IC converts the device number to IDSEL AD signal as follows: device 0 maps to AD[16]; device 1 maps to AD[17]; and so forth. Device numbers 16 through 31 are not valid.

•The compensation values for drive strength and input impedance that are assigned to non-clock forwarded AGP signals are automatically determined and set by the IC during the first compensation cycle after RESET#. Once set, they do not change until the next RESET# assertion.

•Per the link protocol, when the COMPAT bit is set in the transaction, the IC does not ever claim the transac- tion. Such transactions are automatically passed to the other side of the tunnel (or master aborted if the IC is at the end of the chain). This is true of all transactions within address space that is otherwise claimed by the IC, including the space defined by DevB:0x3C[VGAEN].

4.5.2.1AGP Compensation And Calibration Cycles

The AGP PHY includes one compensation circuit for the clock forwarded data signals, A_AD[31:0],

A_CBE_L[3:0], and A_DBI[H, L], and one compensation circuit for the strobes, A_ADSTB[1:0]. Each com- pensation circuit calculates the required rising-edge (P) and falling-edge (N) signal drive strength through a free-running state machine that generates a new value approximately every four microseconds. These values are provided in DevA:0x[50, 54][NCOMP, PCOMP].

Programmable skew values between data signals and strobes are also provided in DevA:0x58.

The compensation values provided to the AGP PHY are software selectable between the calculated compensa- tion values, fixed programmable bypass values, or fixed programmable offsets from the calculated values. Regardless of which value is selected, the value presented to the PHY is never updated until there is a calibra- tion cycle.

Calibration cycles consist of taking control of the AGP bus, updating the AGP PHY compensation values, and then releasing (see DevA:0xA8[PCALCYC]). If enabled by DevA:0xB0[CALDIS], they occur periodically with the period specified by DevA:0xA8[PCALCYC].

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