24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

3.2Tunnel Link Signals

The following are signals associated with the HyperTransportTM links. [B, A] in the signal names below refer to the A and B sides of the tunnel. [P, N] are the positive and negative sides of differential pairs.

Pin name and description

 

IO cell

Power

During

After

 

 

 

type

plane*

reset

reset

 

 

 

 

 

LDTCOMP[3:0]. Link compensation pins for both sides of the tunnel. These are

Analog

VDD-

 

 

designed to be connected through resistors as follows:

 

12B

 

 

Bit

Function

External Connection

 

 

 

 

[0]

Positive receive compensation Resistor to VDD12B

 

 

 

 

[1]

Negative receive compensationResistor to VSS

 

 

 

 

[3, 2]

Transmit compensation

Resistor from bit [2] to bit [3]

 

 

 

 

These resistors are used by the compensation circuit. The output of this circuit is

 

 

 

 

combined with DevA:0x[E8, E4, E0] to determine compensation values that are

 

 

 

 

passed to the link PHYs.

 

 

 

 

 

 

 

 

 

 

LRACAD_[P, N][15:0]; LRBCAD_[P, N][7:0]. Receive link command-address-

Link

VDD12

 

 

data bus.

 

 

input

 

 

 

 

 

 

 

 

LRACLK[1, 0]_[P, N]; LRBCLK0_[P, N]. Receive link clock.

Link

VDD12

 

 

 

 

 

input

 

 

 

 

 

 

 

 

LR[B, A]CTL_[P, N]. Receive link control signal.

Link

VDD12

 

 

 

 

 

input

 

 

 

 

 

 

 

 

LTACAD_[P, N][15:0]; LTBCAD_[P, N][7:0]. Transmit link command-address-

Link

VDD12

Diff

Func.

data bus.

 

 

output

 

High**

 

 

 

 

 

 

LTACLK[1, 0]_[P, N]; LTBCLK0_[P, N]. Transmit link clock.

Link

VDD12

Func.

Func.

 

 

 

output

 

 

 

 

 

 

 

 

LT[B, A]CTL_[P, N]. Transmit link control signal.

Link

VDD12

Diff

Func.

 

 

 

output

 

Low**

 

 

 

 

 

 

 

 

*The signals connected to the A side of the tunnel are powered by VDD12A and the signals connected to the B side of the tunnel are powered by VDD12B.

** Diff High and Diff Low for these link pins specifies differential high and low; e.g., Diff High specifies that the _P signal is high and the _N signal is low.

If one of the sides of the tunnel is not used on a platform then the unconnected link should be treated as fol- lows, for every 10 differential pairs: connect all of the _P differential inputs together and through a resistor to VSS; connect all the _N differential inputs together and through a resistor to VDD12; leave the differential out- puts unconnected. If there are unused link signals on an active link (because the IC is connected to a device with a reduced bit width), then the unused differential inputs and outputs should also be connected in this way.

7

Page 7
Image 7
AMD 8151 specifications Tunnel Link Signals

8151 specifications

The AMD 8151 is a notable member of AMD's family of chipsets, designed to complement the AMD K5 and K6 processors. Released in the late 1990s, this chipset was primarily targeted at performance-driven PCs. The AMD 8151 provided users with an array of features and technologies that enhanced the overall computing experience, making it a popular choice among system builders and enthusiasts at the time.

One of the standout features of the AMD 8151 is its support for a 64-bit data bus. This significant design choice allowed for faster data transfer rates and better communication between the CPU and other critical components, such as memory. The chipset was capable of supporting multiple memory configurations, including ECC (Error-Correcting Code) memory, which enhanced system reliability, particularly for servers and workstations.

In terms of connectivity, the AMD 8151 included several integrated controllers, such as the PCI controller, which facilitated connections to various peripherals and expansion cards. With its support for the PCI bus, users could take advantage of high-speed devices, such as graphics cards, sound cards, and network adapters, enhancing the overall functionality of their systems.

Another important characteristic of the AMD 8151 is its power management capabilities. The chipset featured advanced power management technologies, which allowed systems to use energy more efficiently. This not only helped reduce operational costs but also contributed to less heat production, extending the longevity of the components within the PC.

The AMD 8151 also offered robust support for a range of bus speeds, which provided flexibility for users looking to customize their systems. With a maximum bus speed of 66 MHz, it was well-suited for the processors of its time, ensuring compatibility and optimal performance.

Moreover, the AMD 8151 played a crucial role in the development of 3D graphics capabilities. It was designed to work seamlessly with AMD's 3D graphics technology, which allowed for improved visual performance in gaming and multimedia applications. This made it an appealing choice for users who prioritized graphics performance.

Overall, the AMD 8151 chipset embodied the technological advancements of its era, providing enhanced performance, flexibility, and reliability. It stood as a testament to AMD's commitment to innovation in the computing space, marking a significant chapter in the evolution of PC architecture.