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AMD 8151 specifications Rev 3.03 - July, 3.2Tunnel Link Signals

Models: 8151

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3.2Tunnel Link Signals

24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

3.2Tunnel Link Signals

The following are signals associated with the HyperTransportTM links. [B, A] in the signal names below refer to the A and B sides of the tunnel. [P, N] are the positive and negative sides of differential pairs.

Pin name and description			IO cell	Power	During	After
			type	plane*	reset	reset

LDTCOMP[3:0]. Link compensation pins for both sides of the tunnel. These are			Analog	VDD-
designed to be connected through resistors as follows:				12B
Bit	Function	External Connection
[0]	Positive receive compensation Resistor to VDD12B
[1]	Negative receive compensationResistor to VSS
[3, 2]	Transmit compensation	Resistor from bit [2] to bit [3]
These resistors are used by the compensation circuit. The output of this circuit is
combined with DevA:0x[E8, E4, E0] to determine compensation values that are
passed to the link PHYs.

LRACAD_[P, N][15:0]; LRBCAD_[P, N][7:0]. Receive link command-address-			Link	VDD12
data bus.			input

LRACLK[1, 0]_[P, N]; LRBCLK0_[P, N]. Receive link clock.			Link	VDD12
			input

LR[B, A]CTL_[P, N]. Receive link control signal.			Link	VDD12
			input

LTACAD_[P, N][15:0]; LTBCAD_[P, N][7:0]. Transmit link command-address-			Link	VDD12	Diff	Func.
data bus.			output		High**

LTACLK[1, 0]_[P, N]; LTBCLK0_[P, N]. Transmit link clock.			Link	VDD12	Func.	Func.
			output

LT[B, A]CTL_[P, N]. Transmit link control signal.			Link	VDD12	Diff	Func.
			output		Low**

*The signals connected to the A side of the tunnel are powered by VDD12A and the signals connected to the B side of the tunnel are powered by VDD12B.

** Diff High and Diff Low for these link pins specifies differential high and low; e.g., Diff High specifies that the _P signal is high and the _N signal is low.

If one of the sides of the tunnel is not used on a platform then the unconnected link should be treated as fol- lows, for every 10 differential pairs: connect all of the _P differential inputs together and through a resistor to VSS; connect all the _N differential inputs together and through a resistor to VDD12; leave the differential out- puts unconnected. If there are unused link signals on an active link (because the IC is connected to a device with a reduced bit width), then the unused differential inputs and outputs should also be connected in this way.

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AMD 8151 specifications Rev 3.03 - July, 3.2Tunnel Link Signals

Contents

24888 Rev 3.03 - July Data SheetFigure 1 System block diagram 1.1Device Features2004 Advanced Micro Devices, Inc 24888 Rev 3.03 - JulyTable of Contents Configuration space List of FiguresAMD-8151TM AGP Tunnel Data Sheet Figure 1 System block diagramList of Tables 24888 Rev 3.03 - July Case Temperature3Signal Descriptions 3.1Terminology AMD-8151BL C24888 Rev 3.03 - July 3.2Tunnel Link SignalsAMD-8151TM AGP Tunnel Data Sheet 3.3AGP Signals24888 Rev 3.03 - July 24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet3.5 Power and Ground 3.4 Test and Miscellaneous Signals3.5.1Power Plane Sequencing 4.3Clocking 4.2Reset And Initialization24888 Rev 3.03 - July 4Functional Operation 4.1Overview4.5AGP 24888 Rev 3.03 - July4.4Tunnel Links 4.4.1Link PHY4.5.2Various Behaviors 24888 Rev 3.03 - JulyAGP transaction Link transaction5Registers 5.1Register Overview Figure 2 Configuration space5.1.1Configuration Space 24888 Rev 3.03 - JulyTable 5 Register attributes Table 3 Configuration spaces5.2AGP Device Configuration Registers Table 4 Memory mapped address spacesDescription AGP Device Status And Command RegisterDevA BitsDescription 24888 Rev 3.03 - JulyDevA BitsBits AMD-8151TM AGP Tunnel Data SheetAGP Miscellaneous Control Register DevADescription 24888 Rev 3.03 - JulyAGP PHY Control Register DevADescription AGP PHY Skew Control RegisterDevA BitsBits 24888 Rev 3.03 - JulyAGP Most Recent Request Register DevADescription AGP Command Register24888 Rev 3.03 - July BitsAGP Aperture Size Register AGP Control RegisterBits DescriptionGARTHI GART base address register high Link Command RegisterBits DescriptionDescription Link Configuration And Control Register24888 Rev 3.03 - July Bits24888 Rev 3.03 - July Bits 24888 Rev 3.03 - JulyLink Frequency Capability 0 Register DevA 0xCCBits 24888 Rev 3.03 - JulyLink PHY Compensation Control Registers DevA 0xE8, E4, E0Bits Description Clock Control RegisterAGP Bridge Vendor And Device ID Register 5.3AGP Bridge Configuration RegistersAGP Bridge Status And Command Register 24888 Rev 3.03 - JulyAGP Bridge Memory Base-LimitRegisters DevBBits DescriptionBits 24888 Rev 3.03 - JulyBits DescriptionBits AMD-8151TM AGP Tunnel Data SheetBits Description6Electrical Data 6.1Absolute Ratings Table 6 Absolute maximum ratingsTable 7 Operating ranges 24888 Rev 3.03 - July6.3DC Characteristics Table 8 Current and power consumption24888 Rev 3.03 - July Input low voltage Table 12 AC data for clocks 6.4AC Characteristics24888 Rev 3.03 - July 24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data SheetA PCLK to transmit strobe first strobe edge 7Ball Designations AMD-8151TM AGP Tunnel Data SheetFigure 3 Ball designations 24888 Rev 3.03 - JulySignal name AMD-8151TM AGP Tunnel Data SheetSignal name Signal nameSignal AMD-8151TM AGP Tunnel Data SheetSignal Signal24888 Rev 3.03 - July 8Package SpecificationAMD-8151TM AGP Tunnel Data Sheet Figure 4 Package mechanical drawingTEST 24888 Rev 3.03 - July9Test ModeAMD-8151TM AGP Tunnel Data Sheet NAND tree 2 output signal is STRAPL424888 Rev 3.03 - July 10 Appendix 10.1 Revision History Revision 24888 Rev 3.03 - JulyRevision