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AMD 8151 specifications Rev 3.03 - July, Bits, Description

Models: 8151

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24888 Rev 3.03 - July 12, 2004

AMD-8151TMAGP Tunnel Data Sheet

•Host-initiated transactions inside the windows are routed to the AGP bus.

•PCI transactions initiated on the AGP bus inside the windows are not claimed by the IC.

•Host initiated transactions outside the windows are passed through the tunnel or master aborted if the IC is at the end of a HyperTransport technology chain.

•PCI transactions initiated on the AGP bus outside the windows are claimed by the IC using medium decod-

ing and passed to the host.

So, for example, if IOBASE > IOLIM, then no host-initiated IO-space transactions are forwarded to the AGP bus and all AGP-bus-initiated IO-space (not configuration) transactions are forwarded to the host. If MEM- BASE > MEMLIM and PMEMBASE > PMEMLIM, then no host-initiated memory-space transactions are for- warded to the AGP bus and all AGP-bus-initiated memory-space (not configuration) transactions are forwarded to the host.

DevB:0x1C. Default: 0220 01F1h		Attribute: See below.
Bits	Description

31:30	Reserved.

29	RMA: received master abort. Read; set by hardware; write 1 to clear. 1=The IC received a master
	abort as a PCI master on the AGP bus. Note: this bit is cleared by PWROK reset but not by RESET#.

28	RTA: received target abort. Read; set by hardware; write 1 to clear. 1=The IC received a target abort
	as a PCI master on the AGP bus. Note: this bit is cleared by PWROK reset but not by RESET#.

27	STA: signaled target abort. Read; set by hardware; write 1 to clear. 1=The IC generated a target
	abort as a PCI target on the AGP bus. The IC generates target aborts if it receives a target abort (a non-
	NXA error) response from the host to an AGP bus PCI master transaction request. Note: this bit is
	cleared by PWROK reset but not by RESET#.

26:16	Read only. These bits are fixed in their default state.

15:12	IOLIM. IO limit address bits[15:12]. See DevB:0x[30:1C] above.

11:8	Reserved.

7:4	IOBASE. IO base address bits[15:12]. See DevB:0x[30:1C] above.

3:0	Reserved.

DevB:0x20. Default: 0000 FFF0h		Attribute: Read-write.
Bits	Description

31:20	MEMLIM. Non-prefetchable memory limit address bits[31:20]. See DevB:0x[30:1C] above.

19:16	Reserved.

15:4	MEMBASE. Non-prefetchable memory base address bits[31:20]. See DevB:0x[30:1C] above.

3:0	Reserved.

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AMD 8151 specifications Rev 3.03 - July, Bits, Description

Contents

Data Sheet Figure 1 System block diagram1.1Device Features 24888 Rev 3.03 - July24888 Rev 3.03 - July 2004 Advanced Micro Devices, IncTable of Contents List of Figures AMD-8151TM AGP Tunnel Data SheetFigure 1 System block diagram Configuration spaceList of Tables Case Temperature 3Signal Descriptions 3.1TerminologyAMD-8151BL C 24888 Rev 3.03 - July3.2Tunnel Link Signals 24888 Rev 3.03 - July24888 Rev 3.03 - July 3.3AGP SignalsAMD-8151TM AGP Tunnel Data Sheet AMD-8151TM AGP Tunnel Data Sheet 24888 Rev 3.03 - July3.5.1Power Plane Sequencing 3.4 Test and Miscellaneous Signals3.5 Power and Ground 4.2Reset And Initialization 24888 Rev 3.03 - July4Functional Operation 4.1Overview 4.3Clocking24888 Rev 3.03 - July 4.4Tunnel Links4.4.1Link PHY 4.5AGP24888 Rev 3.03 - July AGP transactionLink transaction 4.5.2Various BehaviorsFigure 2 Configuration space 5.1.1Configuration Space24888 Rev 3.03 - July 5Registers 5.1Register OverviewTable 3 Configuration spaces 5.2AGP Device Configuration RegistersTable 4 Memory mapped address spaces Table 5 Register attributesAGP Device Status And Command Register DevABits Description24888 Rev 3.03 - July DevABits DescriptionAMD-8151TM AGP Tunnel Data Sheet AGP Miscellaneous Control RegisterDevA Bits24888 Rev 3.03 - July AGP PHY Control RegisterDevA DescriptionAGP PHY Skew Control Register DevABits Description24888 Rev 3.03 - July AGP Most Recent Request RegisterDevA BitsAGP Command Register 24888 Rev 3.03 - JulyBits DescriptionAGP Control Register BitsDescription AGP Aperture Size RegisterLink Command Register BitsDescription GARTHI GART base address register highLink Configuration And Control Register 24888 Rev 3.03 - JulyBits Description24888 Rev 3.03 - July 24888 Rev 3.03 - July Link Frequency Capability 0 RegisterDevA 0xCC Bits24888 Rev 3.03 - July Link PHY Compensation Control RegistersDevA 0xE8, E4, E0 BitsClock Control Register Bits Description5.3AGP Bridge Configuration Registers AGP Bridge Status And Command Register24888 Rev 3.03 - July AGP Bridge Vendor And Device ID RegisterDevB BitsDescription AGP Bridge Memory Base-LimitRegisters24888 Rev 3.03 - July BitsDescription BitsAMD-8151TM AGP Tunnel Data Sheet BitsDescription BitsTable 6 Absolute maximum ratings Table 7 Operating ranges24888 Rev 3.03 - July 6Electrical Data 6.1Absolute Ratings24888 Rev 3.03 - July Table 8 Current and power consumption6.3DC Characteristics Input low voltage 24888 Rev 3.03 - July 6.4AC CharacteristicsTable 12 AC data for clocks A PCLK to transmit strobe first strobe edge AMD-8151TM AGP Tunnel Data Sheet24888 Rev 3.03 - July AMD-8151TM AGP Tunnel Data Sheet Figure 3 Ball designations24888 Rev 3.03 - July 7Ball DesignationsAMD-8151TM AGP Tunnel Data Sheet Signal nameSignal name Signal nameAMD-8151TM AGP Tunnel Data Sheet SignalSignal Signal8Package Specification AMD-8151TM AGP Tunnel Data SheetFigure 4 Package mechanical drawing 24888 Rev 3.03 - July24888 Rev 3.03 - July 9TestMode TEST24888 Rev 3.03 - July NAND tree 2 output signal is STRAPL4AMD-8151TM AGP Tunnel Data Sheet Revision 24888 Rev 3.03 - July10 Appendix 10.1 Revision History Revision