Cisco Systems Cisco 12006, Cisco 12406 - page 224

Chapter 5 Field Diagnostics for the Cisco 12000 Series Router
FPGA Overview
5-4
Cisco 12006 and Cisco 12406 Router Installation and Configuration Guide
OL-11497-03
The following sample Cisco IOS boot text shows an FPGA upgrade message in
bold text.
*Aug 19 14:51:06 UTC: %MBUS-6-FABCONFIG: Switch Cards 0x1F (bitmask)
Primary Clock is CSC_1
Fabric Clock is Redundant
Bandwidth Mode : Full Bandwidth
*Aug 19 14:51:23 UTC: %MBUS-6-NO_FPGA_IMG: FPGA image is not
appropriate or corrupted for slot 0. Please run Field Diagnostics
image on slot 0 to upgrade the FPGA image.
*Aug 19 14:51:31 UTC: %GRPGE-6-SYNC_LOSS: Interface
GigabitEthernet2/0: Loss of Sync
*Aug 19 14:51:31 UTC: %GRPGE-6-RX_LOS: Interface
GigabitEthernet2/0: Detected RX Loss of Signal
SLOT 2:00:00:12: %SYS-5-RESTART: System restarted --
Cisco Internetwork Operating System Software
IOS (tm) GS Software (GLC1-LC-M), Experimental Version
12.0(20030605:093502) [mliflian-25-thr-work-nog-lke 115]
Copyright (c) 1986-2003 by cisco Systems, Inc.
Compiled Tue 19-Aug-03 17:33 by mliflian
When this message is received, the Cisco 12000 Series Router field diagnostics
are used to update the Flash memory with the new image. When using field
diagnostics to update the FPGA, no actual test is initiated, only an update to the
FPGA code. See the “Upgrade the FPGA Image on a Line Card” section on
page 5-7.
When field diagnostics run, the target line card stops passing traffic, but the rest
of the router continues passing traffic normally. The line card is loaded with the
field diagnostics program, the Flash memory update is run, and, if successful, the
card reboots to Cisco IOS. The entire process takes approximately 2 minutes per
line card and must be done one line card at a time. It is a good practice to wait
about 30 seconds after Cisco IOS reloads on the line card before updating the next
line card. This gives the router a chance to synchronize all its internal functions.
The following sample output shows the process involved in updating the FPGA
code on a line card in slot 0.
router# diag 0 verbose update-fpgas
Running DIAG config check
Fabric Download for Field Diags chosen: If timeout occurs, try
'mbus' option.
Verbose mode: Test progress and errors will be displayed
UUT will update FPGA's flash
Running Diags will halt ALL activity on the requested
slot.[confirm]
Router#
Launching a Field Diagnostic for slot 0