Chapter 5 Instruction Specifications

5-8

R7F4
R7F3
R7F2
R7F1
R7F0
Process
time
(µ s)
Classification
Item number
Ladder symbol
Instruction
symbol
Instruction
name Process descriptions I/O types used
DER ERR SD V C MICRO-EH
Steps
Remarks
Relational expression
21 d=s1 <= s2 Relational
expression
When s1 < s2, d 1
When s1 s2, d 0
[Word]
d: Y, R, M
s1, s2: WX, WY,
WR, WM, Timer
Counter,
Constant
[Double word]
d: Y, R, M
s1, s2: DX, DY,
DR, DM,
Constant
zzzzz 40
71
4
6
Upper
case: W
Lower
case: DW
22 d=s1 S<= s2 Signed
Relational
expression
When s1 s2, d 1
When s1 > s2, d 0
s1 and s2 are compared as
signed 32-bit binary.
[Double word]
d: Y, R, M
s1, s2: DX, DY,
DR, DM,
Constant
50 6

5. Application instructions

R7F4
R7F3
R7F2
R7F1
R7F0
Process
time
(µ s)
Classification
Item number
Ladder symbol
Instruction
symbol
Instruction
name Process descriptions I/O types used
DER ERR SD V C MICRO-EH
Steps
Remarks
1 BSET(d, n) Bit set n 0
d
Sets 1 to bit n.
zzzzz 26
35
3
3
Upper
case: W
Lower
case: DW
2 BRES(d, n) Bit reset n 0
d
Sets 0 to bit n.
zzzzz 29
38
3
3
Upper
case: W
Lower
case: DW
Bit operations
3BTS(d, n) Bit test n 0
d
Acquires the value in bit n
to C (R7F0).
[Word]
d: WY, WR,
WM, TC
n(0-15): WX,
WY, WR, WM,
TC,
Constant
[Double word]
d: DY, DR, DM
n(0-31): WX,
WY, WR, WM,
TC,
Constant
zzzz 31
38
3
3
Upper
case: W
Lower
case: DW
4 SHR(d, n) Shift right
Shifts right by n bits.
zzzz 38
46
3
3
Upper
case: W
Lower
case: DW
Shift/rotate
5 SHL(d, n) Shift left
Shifts left by n bits.
[Word]
d: WY, WR,
WM, TC
n: WX, WY, WR,
WM, TC,
Constant
zzzz 38
46
3
3
Upper
case: W
Lower
case: DW
6 ROR(d, n) Rotate right
Rotates right by n bits.
[Double word]
d: DY, DR, DM
n: WX, WY, WR,
WM, TC,
Constant
zzzz 47
75
3
3
Upper
case: W
Lower
case: DW
7 ROL(d, n) Rotate left
Rotates left by n bits.
*C: R7F0
SD: R7F2
zzzz 46
54
3
3
Upper
case: W
Lower
case: DW
8 LSR(d, n) Logical
shift right
Shifts right by n bits.
zzzz 36
45
3
3
Upper
case: W
Lower
case: DW
9 LSL(d, n) Logical
shift left
Shifts left by n bits.
zzzz 36
45
3
3
Upper
case: W
Lower
case: DW
0
C
C
d
Cd
0C
d
0
Cd
←←
1
SD C
d
CSD
d