Programming Model
Chip-Select Logic 6-19
ECDS
Bit 14 Early Cycle Detection for Static
Memory—This bit advances the chip-select
signals for SRAM, ROM, or flash memory. It
allows more setup time for slow memory with-
out adding CPU wait states.
0 = Disabled.
1 = Enabled.
ECDT
Bit 13 Early Cycle Detection Type—When the mas-
ter enable for early cycle detection is on (that
is, ECDD= 1), this bit selects what signal from
the CPU is used to trigger the bus cycle.
0 = Use the early ASB from the CPU as the
triggering signal for early cycle detection.
1 = Use the TSCAE from the CPU as the
triggering signal for early cycle detection.
EASP
Bit 12 Early ASB Delay Processing for Static
Memory Early Cycle Detection—To prevent
the early ASB signal from the CPU from being
asserted before a valid address is present
from the CPU, the early ASB can be pro-
grammed so it is delayed before going to the
chip-select generator. This bit must be pro-
grammed appropriately when early ASB is
chosen as the early cycle detection signal.
0 = Use selectable delay chain as the delay
processing method.
1 = Use negative CPU edge synchronization as
the delay processing method (default
setting).
Reserved
Bits 11–10 Reserved These bits are reserved and should be set to
0.
EASDLY[1:0]
Bits 9–8Early ASB Delay Value—When delay chain is
chosen as the delay processing method for
early ASB (that is, the EASP bit is clear), these
bits select the level of the delay element for the
early ASB to get through.
00 = No delay.
01 = 1 level.
10 = 2 levels.
11 = 3 levels.
Reserved
Bits 7–0Reserved These bits are reserved and should be set to
0.

Table 6-13. Chip-Select Control Register 2 Description (Continued)

Name Description Setting