Motorola MC68VZ328 4.2 CGM Operational Overview

CGM Operational Overview
Clock Generation Module and Power Control Module 4-3
4.2 CGM Operational Overview
The CGM consists of six major parts, as shown in the simplified block diagram in Figure 4-1. The clock
source for the CGM is a crystal oscillator that is comp rised of an external crystal connected to the internal
XTAL oscillator circuit. The output of the XTAL oscillator is the CLK32 signal, whose frequency is
determined by the frequency of the external crystal. The CLK32 clock signal serves as a source for the
PLL and many other modules within the MC68VZ328.
The output frequency of the PLL (PLLCLK) is determined by the frequency of CLK32 and by the values
of the PC and QC fields of the PLL frequency select register (PLLFSR). The output of the PLL is applied
to a divider chain composed of two prescalers. The PLLCLK clock is first input into prescaler 1. Its outp ut
frequency is selected by the prescaler select 1 (PRESC1) bit in the PLLCR. The output of the prescaler 1
(PR1CLK) is applied to prescaler 2, whose output frequency (DMACLK) is controlled by the prescaler
select 2 (PRESC2) bit in the PLLCR. The DMACLK signal is applied to the LCD controller in the
MC68VZ328 and also serves as the clock source for the LCD clock divider and the SYSCLK divider.
The output of the LCD clock divider is LCDCLK, whose frequency is controlled by the LCD clock
selection (LCDCLK) field in the PLLCR. The LCDCLK signal is only used by the LCD controller. The
SYSCLK divider produces a SYSCLK clock signal that is used throughout the MC68VZ328. SYSCLK is
also used as the CPU clock signal (CPUCLK) by the internal FLX68000 CPU. SYSCLK is the only
CGM-generated clock signal that can be made available to external devices via the buffered output of the
clock out/Port F bit 2 pin (CLKO/PF2). See Section10.4.7.3, “Port F Dedicated I/O Functions,” on
page 10-26 for more information. The output is available when the clock enable bit of the PLLCR is
enabled and bit 2 in the Port F select register (PFSEL) is cleared.
Figure 4-1. Clock Generation Module (CGM) Simplified Block Diagram
DSPL
XTAL
Oscillator
EXTAL
XTAL
PLL
PC QC
PLLFSR
SYSCLK
LCDCLK SEL SYSCLK SELPRESC2 CLKEN
CLK32
LCD Clock
Divider
SYSCLK
Divider
CLKO/
PF2
Prescaler 2
PLLCR
CLK32
DMACLK
LCDCLK
Enable
Buffer
PRESC1
Prescaler 1
PR1CLK
PLLCLK