Motorola MC68VZ328 10.3.2 Data Flow to the I/O Module, 10.3.3 Operating a Port as GPIO

I/O Port Operation
I/O Ports 10-5
Figure 10-2. I/O Port Operation
For example, if Figure10-2 represents the D0 bit of Port E, when the SEL0 in the select register is cleared,
the “data from module” line is connected to the serial peripheral interface module’s TXD signal
(SPITXD). Because SPITXD is output-only, the MC68VZ328 asserts the “output enable from module”
line, thus enabling the output and disabling the “data to module” line. As long as the SELx bit of the port’s
select register is clear (the default is set at reset), the SPI module pin function is enabled. Bit D0 of Port E
is the master SPMTXD signal. The SPI module controls the direction of data flow for the pin, which is
always output. When the dedicated module controls the port, the direction register is ignored. There are a
few exceptions that are described in the individual port programming sections that follow.
10.3.2 Data Flow to the I/O Module
An example of data flow to the I/O module is the D1 bit of Port E . Thi s si gna l’s function is the SPI’s RXD
(SPIRXD) signal. In this case, SPIRXD is input-only; thus, the chip negates the “output enable from
module” line, and the “data from module” line is not disabled (see Figure10-2). The “data to module”
signal is connected to the SPIRXD input of the SPI.
10.3.3 Operating a Port as GPIO
While the SELx bit is set (if the DIRx bit of the PxDIR is 1), data written to the port’s data register is
presented to the pin. If the DIRx bit in the direction register is 0 (input), data present on th e pi n is sampl ed
and presented to the CPU when a read cycle is executed. While the DIRx bit is 0 (output), the actual pin
level is presented during write accesses. This may not be the same as the data that was written if the pin is
overdriven. To prevent data loss when changing from one mode to another, the intended data should be
written to the PxDATA register before entering the selected mode.
Pad
Data Register
Direction Register
Select Register
0
SEL
1
Pull-up Enable Register
0
SEL
1
Data to
Module
Signal
Data from
Module
Output
Signal
Enable from
Module
Signal
Pad Buffer