Motorola MC68VZ328 , 10.4.2.2 Port B Data Register

Programming Model
I/O Ports 10-9
PBDIR Port B Direction Register 0x(FF)FFF408
10.4.2.2 Port B Data Register
The settings for the PBDATA bit positions are shown in Table10-8.
PBDATA Port B Data Register 0x(FF)FFF409
Port B is multiplexed with chip-select, DRAM control, TIN/TOUT, and PWM dedicated I/O signals.
These pins can be programmed as GPIO when these other assignments are not used.
These bits control or report the data on the pins while the associated SELx bits are high. While the DIRx
bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the Dx bits report
the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as inputs will
accept the data, but the data written to each cannot be accessed unt il t he cor respond ing pin i s conf igure d as
an output. The actual value on the pin is reported when these bits are read, regardless of whether they are
configured as input or output.
BIT 7654321BIT 0
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
TYPE rw rw rw rw rw rw rw rw
RESET 00000000
0x00
Table 10-7. Port B Direction Register Description
Name Description Setting
DIRx
Bits 7–0 Direction—These bits control the direction of the pins. They reset to 0. With the exception of bit 6, if a bit is selected as a dedicated
I/O in PBSEL, the DIR bit is ignored.
0 = Inputs
1 = Output
BIT 7654321BIT 0
D7 D6 D5 D4 D3 D2 D1 D0
TYPE rw rw rw rw rw rw rw rw
RESET
11111111
0xFF*
*Actual bit value depends on external circuits connected to pin.
Table10-8. Port B Data Register Description
Name Description Setting
Dx
Bits 7–0 Data—These bits reflect the status of the I/O signal in an
8-bit system.
0 = Drives the output signal low when DIRx is set to 1 or the
external signal is low when DIRx is set to 0
1 = Drives the output signal high when DIRx is set to 1 or the
external signal is high when DIRx is set to 0