Motorola MC68VZ328 4.5.1 Operating the PCM

Introduction to the Power Control Module

Clock Generation Module and Power Control Module 4-11

4.5.1 Operating the PCM

The power control module has four modes of operation: normal, burst, doze and sleep. In normal mode, the

PCM is off. The MC68VZ328 enters burst mode when the PCM is enabled. In burst mode, the PCM

controls the burst width of the CPUCLK signal to the CPU. If the burst width of the CPU clock is reduced

to zero, CPUCLK is disabled and the MC68VZ328 is in doze mode. The lowest power mode setting is

sleep mode. It is entered by setting the disable PLL (DISPLL) bit in the PLLCR, which disables the PLL

and thus disables every clock signal in the CGM except CLK32. Section4.5.1.1, “Normal Mode,” through

Section4.5.1.4, “Sleep Mode,” give detailed information about each of the four power modes.

After reset, the PCM is disabled, the CPU clock runs continuously, and the MC68VZ328 consumes

maximum power. This is normal mode.

Setting the PCEN bit in the power control register (PCTRL) enables the PCM, causing the clock burst

width of the CPU clock to be under the control of the PCTLR WIDTH settings in increments of 3 percent

(one thirty-first of a cycle). Initially, the burst width is set to 100 percent. Software can then change the

burst width to a lower value, and the clock is applied to the CPU in bursts. The burst-width register ca n be

programmed for burst widths of any value between zero thirty-firsts and thirty-one thirty-firsts. This

effectively produces a system clock with a variable burst width (and power dissipation) betwee n 3 per ce nt

and 100 percent in incremental steps of 3 percent.

When the PCM is enabled, if a wake-up event is received, the PCM is immediately disabled, restoring the

continuous CPU clock. It is the responsibility of the wake-up service routine to reenable the PCM.

Setting the width field of PCTLR to %00000 reduces the burst width of the CPU clock to zero, causing the

MC68VZ328 to enter doze mode. As with burst mode, the CPUCLK is immediately enabled when it

receives a wake-up event. At the end of the service routine, the PCM can be reenabled with a width of

%00000, putting the CPU back into doze mode. Once the CPU is placed in doze mode, only a wake-up

event or hardware reset will reenable it .

NOTE:

The most effective power-control strategy is to run the CPU in normal

mode until CPU action is not needed and then to enter doze mode by

writing 0x80 into the PCTLR. This disables the CPU clock at the earliest

possible moment, but allows the CPU to immediately respond to wake-up

events. The peripheral devices, including the LCD controller, are not

affected by the PCM.