Motorola MC68VZ328 19.3.5 Chip-Select Timing Trim, 19.3.6 DRAM Read Cycle 16-Bit Access (CPU Bus Master)

19-8 MC68VZ328 User’s Manual 
AC Electrical Characteristics
19.3.5 Chip-Select Timing Trim
Figure 19-5 shows the timing diagram for the chip-select timing trim. The signal values and units of
measure for this figure are found in Table19-7. For detailed information about the individual signals, see
Chapter 6, “Chip-Select Logic.”
Figure 19-5. Chip-Select Timing Trim Timing Diagram
19.3.6 DRAM Read Cycle 16-Bit Access (CPU Bus Master)
Figure 19-6 on page19-9 shows the DRAM read cycle timing diagram for 16-bit access (CPU bus master).
The signal values and units of measure for this figure are found in Table19-8 on page 19-9. Detailed
information about the operation of individual signals can be found in Chapter7, “DRAM Controller,” and
Chapter 6, “Chip-Select Logic.”
Table 19-7. Chip-Select Timing Trim Timing Parameters
Number Characteristic (3.0 ± 0.3)V Unit
Minimum Maximum
1 CLKO high to CSx asserted (bit ECDS= 0) —10ns
2 CLKO low to CSx asserted (bit ECDS = 1) — 10 ns
3UWE
/LWE negated before CSx is negated (bit WPEXT= 0) 10 20 ns
4UWE
/LWE negated before CSx is negated (bit WPEXT= 1) 40 50 ns
CSx
UWE/LWE
CLKO
S0 S2 S4 WS S6 S0
CSx
1
UWE/LWE
2
3
4