Motorola MC68VZ328 19.3.7 DRAM Write Cycle 16-Bit Access (CPU Bus Master)

19-10 MC68VZ328 User’s Manual 
AC Electrical Characteristics
19.3.7 DRAM Write Cycle 16-Bit Access (CPU Bus Master)
Figure 19-7 shows the DRAM write cycle timing diagram for 16-bit access (CPU bus master). The signal
values and units of measure for this figure are found in Table19-9 on page 19-11. Detailed information
about the operation of individual signals can be found in Chapter7, “DRAM Controller,” and Chapter 6,
“Chip-Select Logic.”
Figure 19-7. DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Diagram
12 CASx asserted before column address
invalid 50 —ns
13 RASx negated after CASx is negated 28 — ns
14 RASx precharge time (SLW=0,1) 58,118 — ns
Note: RASx stands for RAS0 and RAS1. CASx stands for CAS0 and CAS1.
Note: MSW is bit 5, SLW is bit 3, and BC[1:0] comprises bits 13–12 in the DRAMC register. When the table
identifies these bits, the sequence of their listed values corresponds to the sequence of timing data provided.
Table 19-8. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Parameters (Continued)
Number Characteristic (3.0 ± 0.3)V Unit
Minimum Maximum
MD[12:0]
RASx
CASx
OE
D[15:0]
DWE
14
5
12
6 8 13
7
14
2
3
11
910
ColumnRow Row