2-4 MC68VZ328 User’s Manual
Clock and System Control Signals
2.2 Power and Ground Signals
The MC68VZ328 microprocessor has three types of power pins. They are VDD, VSS, and LVDD.
•V
DD—External power supply to drive all I/O pins and for the internal voltage regulator. It is
recommended to place a 0.1µF bypass capacitor close to each of these pins.
•V
SS—Signal return pin for both digital and analog circuits.
•LV
DD—Internal voltage regulator output signal that is used by t he internal ci rcuitry . The LVDD pins
should not be used as an external circuit power supply due to current supply limitations. Each
package has unique bypass capacitor requirements. The TQFP package requires that an external
bypass capacitor circuit of 0.01µF and 0.0001 µF (in parallel) be placed close to each of the LVDD
pins, except pin 35, which requires a 270nF and a 0.0001 µF bypass capacitor. The PBGA has a
single LVDD pin (M1) requiring only a 270nF and a 0.0001 µF bypass capacitor.
NOTE:
For maximum noise immunity, ensure that external bypass capacitors are
placed as close to the pins as possible.
2.3 Clock and System Control Signals
There are four clock and system control signals.
• EXTAL—External Clock/Crystal. This input signal connects to the e xterna l lo w frequenc y crysta l.
The MC68VZ328 microprocessor supports both a 32.768kHz and a 38.4 kHz crystal frequency.
For a 32.768kHz input, the internal phase-locked loop generates a PLLCLK signal that passes
through two prescalers, and the resulting output (DMACLK and SYSCLK) clock is 16.58 MHz.
Figure 2-2 illustrates how a crystal is usually connected to the MC68VZ328. For specific circuit
design values, see Figure4-2 on page 4-4.
Figure 2-2. Typical Crystal Connection
• XTAL—Crystal. This output signal connects the on-chip oscillator output to an external crystal.
• CLKO/PF2—Clock Out or bit 2 of Port F. This output clock sig nal is deri ved from the on-chip c lock
oscillator and is internally connected to the clock output of the internal CGM. This signal is
provided for external reference. The output c a n be disabled in the PLL control register to reduce
power consumption and electromagnetic emission. See Section4.4.1, “PLL Control Register,” on
page 4-8 for more information. The CLKO/PF2 signal defaults to the Port F pin 2 input signal. For
detailed information, refer to Section10.4.7.3, “Port F Dedicated I/O Functions,” on page 10-26.
•R
ESET—Reset. This active low, Schmitt trigger input signal resets the entire MC68VZ328
processor (CPU and peripherals). The threshold of this Schmitt trigger device is 1.2V high and
0.8 V low . After the MC68VZ328 po wers up, this reset input si gnal should be dr ive n low for at least
EXTAL XTAL
32.768kHz or 38.4 kHz
C2
C1