Motorola MC68VZ328 13.4 SPI 2 Overview

SPI 2 Overview
Serial Peripheral Interface 1 and 2 13-11
SPISPC SPI 1 Sample Period Control Register 0x(FF)FFF70A
13.4 SPI 2 Overview
This section discusses how SPI 2 can be used to communicate with external devices, such as EEPROMs,
analog-to-digital converters, and other peripherals. The SPI 2 module is a 3- or 4-wire system, depending
on whether you are using unidirectional or bidirectional communication mode. It provides the clock for
data transfer and can only function as a master device. It is fully compatible with the serial peripheral
interface on Motorola’s 68HC05 and 68HC11 microprocessors. Figure13-3 shows the SPI 2 block
diagram.
Figure 13-3. SPI 2 Block Diagram
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0
CSRC WAIT
TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET 0 00000000000000 0
0x0000
Table 13-6. SPI 1 Sample Period Control Register Description
Name Description Setting
CSRC
Bit 15 Counter Clock Source—This bit selects the clock source for the sample period counter. 0 = SPICLK1 clock 1 = CLK32 (32.68 kHz normal crystal used)
WAIT
Bits 14–0 Wait—Number of clock periods inserted between data transactions in master mode 0000 = 0 clocks 0001 = 1 clock
0002 = 2 clocks
.
.
.
7FFF = 32767 clocks (approximately 1 second)
SPICLK2
Control
MPU Interface
SPIRXD
SPITXD
MSB
Clock
Generator
Shift Register