Programming Model
Pulse-Width Modulator 1 and 2 15-5
FIFOAV
Bit 5 FIFO Available—This bit indicates that the
FIFO is available for at least 1 byte of sample
data. Data bytes can be loaded into the FIFO
as long as this bit is set. If the FIFO is loaded
while this bit is cleared, the write will be
ignored.
0 = FIFO not available.
1 = FIFO available (default).
EN
Bit 4 Enable—This bit enables or disables the
pulse-width modulator. If this bit is not enabled,
writing to other pulse-width modulator registers
is ignored.
0 = Disabled*
1 = Enabled**
REPEAT
Bits 3–2 Sample Repeats—These write-only bits select
the number of times each sample is repeated.
The repeat feature reduces the interrupt over-
head, thus reducing CPU loading when audio
data is played back at a higher rate, and allows
the use of a lower cost low-pass filter. For
example, if the audio data is sampled at 8kHz
and the data is played back at 8kHz again, an
8kHz humming noise (carrier) is generated
during playback. To filter this carrier, a
high-quality low-pass filter is required. For a
higher playback rate, it is possible to recon-
struct samples at 16 kHz by using the sample
twice. This method shifts the carrier from an
audible 8kHz to a less sensitive 16 kHz fre-
quency range, thus providing better
sound-quality output.
00 = No samples are repeated (play sample
once). This is the default.
01 = Repeat one time (play sample twice).
10 = Repeat three times (play sample four
times).
11 = Repeat seven times (play sample eight
times).
CLKSEL
Bits 1–0 Clock Selection—This field selects the output
of the divider chain. The approximate sampling
rates are calculated using a 16.58MHz clock
source (PRESCALER= 0 and
PERIOD= default).
00 = Divide by 2. Provides an approximate
32 kHz sampling rate (default).
01 = Divide by 4. Provides an approximate
16 kHz sampling rate.
10 = Divide by 8. Provides an approximate
8kHz sampling rate.
11 = Divide by 16. Provides an approximate
4kHz sampling rate.
Note:
*When the pulse-width modulator is disabled, it is in low-power mode, t he output p in is force d to 0, and t he follow ing
events occur:
• The clock prescale r is reset and frozen.
• The counter is reset and frozen.
• The FIFO is flushed.
**When the pulse-width modulator is enabled, it begins a new period, and the following events occur:
• The output pin is set to start a new period.
• The prescaler and counter are released and begin counting.
• The IRQ bit is set, thus indicating that the FIFO is empty.

Table 15-1. PWM 1 Control Register Description (Continued)

Name Description Setting