Motorola MC68VZ328 16.1 ICE Operation

16-2 MC68VZ328 User’s Manual 

ICE Operation

16.1 ICE Operation

The in-circuit emulation module’s operation consists of the following tasks:

• Entering emulation mode

• Detecting breakpoints

• Using the signal decoder

• Using the interrupt gate module

• Using the A-line insertion unit

The in-circuit emulation module latches the state of the EMUIRQ signal on the rising edge of the RESET

signal. To put the MC68VZ328 in emulation mode, the EMUIRQ signal must be driven low (externally)

during system reset. After system reset, EMUIRQ becomes a falling edge trigger signal, which genera te s a

level 7 interrupt when active. For emulati on mode, the CSA0 signal is not asserted for reset fetch, since it

is in normal operation mode. The in-circuit emulation module internally generates a reset vector to the

processor on reset vector fetch cycles.

This hard-coded reset vector is PC= 0xFFFC0020 and SSP= 0xFFFCFFFC, which means that the

monitor or boot code must start at 0xFFFC0020. The EMUCS signal is designed to cover system memory

space from 0xFFFC0000 to 0xFFFCFFFF, and it is an 8-bit data bus width chip-select signal. If EMUIRQ

is logic high during system reset, the in-circuit emulation module is disabled and the MC68VZ328 begins

another operation mode.

The execution breakpoint detector has one 32-bit address comparator and one control signal comparator.

When the in-circuit emulation module is configured to operate in single breakpoint mode, in which

EMUBRK is an output, the generation of the EMUBRK signal is internally qualified by the AS si gnal. The

active time for this signal will vary, depending on the setting and width (wait state) of the bus cycle. The

EMUBRK signal is asserted throughout the address matched cycle. When the in-circuit emulation module

is in multiple breakpoint mode, EMUBRK is an input that is asserted by the external address comparator.

The external address comparator will compare the lower address while the internal comparator, with

masking, compares the hidden address signals. The EMUBRK signal, together with the internal compare

result, generates the match signal to the break p oint insertion unit.

Since the processor does not have built-in emulation support, the execution breakpoint is implemented

external to the core and will use the A-line instr uction and level 7 interrupt. To accurately catch the

execution breakpoint, the in-circuit emulation module inserts the 0xA0000 opcode at the location where a

breakpoint is set. For more information regarding the insertion mechanism, refer to Section16.1.5, “Using

the A-Line Insertion Unit.” When the 0xA000 opcode is being executed, which means the breakpoint is

reached, an exception vector fetch for an A-line exception will occur. At this point, EMUBRK is asserted

to stop the process and switch control to the emulation monitor (selected by the EMUCS signal).

An exception vector fetch for an A-line exception consists of two consecutive word reads at addresses

0x28 and 0x2A. The A-line exception vector fetch will cause an IRQ7 asser tion if a b reakpo int i s a ctiva ted

in emulation mode. However, normal memory reads to these two words will not cause an IRQ7 assertion.