Motorola MC68VZ328 19.3.2 Chip-Select Read Cycle Timing

AC Electrical Characteristics
Electrical Characteristics 19-3
Figure 19-1. CLKO Reference to Chip-Select Signals Timing Diagram
19.3.2 Chip-Select Read Cycle Timing
Figure 19-2 on page19-4 shows the read cycle timing used by chip-select. The signal values and units of
measure for this figure are found in Table19-4 on page 19-4. For detailed information about the individual
signals, see Chapter 6, “Chip-Select Logic.”
Table 19-3. CLKO Reference to Chip-Select Signals Timing Parameters
Number Characteristic (3.0 ± 0.3) V Unit
Minimum Maximum
1 CLKO high to CSx asserted —10ns
2CLKO low to CSx
negated — 12 ns
3 CLKO high to RASx asserted — 10 ns
4 CLKO high to RASx negated — 12 ns
5 CLKO high to CASx asserted — 10 ns
6 CLKO high to CASx negated — 12 ns
CLKO
S0 S2 S4 WS S6 S0
CSx
RASx
CASx
1
3
5 6
2
4