Motorola MC68VZ328 12.2.3 Timer Compare Registers 1 and 2

Programming Model
General-Purpose Timers 12-9
12.2.3 Timer Compare Registers 1 and 2
Each timer compare (TCMPx) register contains the value that is compared with the counter. A compare
event is generated when the counter matches the value in this register. This register is set to 0xFFFF at
system reset. The settings for the registers are described in Table12-4.
TCMP1 Timer Compare Register 1 0x(FF)FFF604
TCMP2 Timer Compare Register 2 0x(FF)FFF614
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0
COMPARE
TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET 1 111111111111111
0xFFFF
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0
COMPARE
TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET 1 1 1 1 1 1111111111 1
0xFFFF
Table 12-4. Timer Compare Register Description
Name Description Setting
COMPARE
Bits 15–0 Compare Value—Write this field’s value to generate a compare event when the counter
matches this value.
This field has a valid range 0x0000 to 0xFFFF.