Motorola MC68VZ328 4.3.2.2 PLL Frequency Selection, 4.3.2.3 PLLCLK Frequency Selection Programming Example

4-6 MC68VZ328 User’s Manual 
Detailed CGM Clock Descriptions
4.3.2.2 PLL Frequency Selection
Using the default settings for the PC and QC fields of the PLLFSR and a CLK32 input frequency of
32.768 kHz produces a PLLCLK output of 66.322MHz. For a 38.400 kHz crystal, the same default
settings produce a 77.722MHz PLLCLK. The PLLCLK clock is phase locked to the CLK32 clock input
signal.
WARNING:
The value of prescaler 1 must always be set to divide-by-two to prevent
DMACLK and SYSCLK from operating beyond their design limits.
The PLL uses a dual-modulus counter to multiply the CLK32 frequency before it is input to the prescaler
and the rest of the divider chain. Dual-modulus counters opera te di fferently from other counters in that the
overall multiplication ratio depends on two separate values, PC and QC.
In the following equation, the value of Q is defin ed as 1< Q<14, and the value of P is defined as
P>Q+1.
Eqn. 4-2
For example, if Q = 3 and P = 71, then the following equations obtain:
Multiplier= 2 * (14 (71 + 1) + 3 + 1) = 2 * (1008 + 4) = 2024
2024 * 32.768kHz = 66.322432 MHz
The default multiplier value is 2024. Using any multiplier equal to or greater than 794 (decimal) allows
changing the PLLCLK in 32.768kHz or 38.4 kHz steps. The minimum PC and QC values are P= 0x1B
and Q =0x04 (which produce a multiplier of 794 decimal).
4.3.2.3 PLLCLK Frequency Selection Programming Example
Example 4-1 on page 4-7 demonstrates the recommended sequence of events to change the PLLCLK
frequency. The assumptions are:
• All peripherals have been disabled using chip-select. See Chapter6, “Chip-Select Logic,” for
details.
• SYSCLK is operating at the highest possible frequency (SYSCLK SEL= 100).
In Example4-1, the variable NEWFREQ is the new frequency value (P and Q values) to be programmed.
The MC68VZ328 is placed in sleep mode before the stop command. See Section4.5.1.4, “Sleep Mode,”
for detailed information about sleep modes. This routine enables the timer to wake up the PLL after 96
CLK32 periods. When the PLL wakes up, it will be at the new frequency. The interrupt service routine for
the temporary timer interrupt should clear the timer interrupt and then return. In addition, the PLLCLK
should only be changed during an early phase of the boot-up sequence.
NOTE:
Example4-1 is designed for clarity, and is not necessarily efficient.
Multiplier 2 14 P 1+
()
Q1++
()
=