Motorola MC68VZ328 19.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)

19-16 MC68VZ328 User’s Manual 
AC Electrical Characteristics
19.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access
(LCD Bus Master)
Figure 19-12 shows the timing diagram for the LCD DRAM DMA cycle for 16-bit Fast Page Mode mode
access (LCD bus master). The signal values and units of measure for this figure are found in Table19-14.
Detailed information about the operation of individual signals can be found in Chapter 7, “DRAM
Controller,” and Chapter8, “LCD Controller.”
Figure 19-12. LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
Timing Diagram
Table 19-14. LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
Timing Parameters
Number Characteristic (3.0 ± 0.3)V Unit
Minimum Maximum
1 Row address valid to RASx asserted 45 —ns
2DWE
negated before row address valid 0 — ns
3OE
asserted before RASx asserted 0 — ns
4 RASx asserted before row address invalid
(MSW= 0 ,1) 12,27 — ns
5 Column address valid to CASx asserted
(MSW= 0 ,1) 10,25 — ns
6 RASx asserted to CASx asserted (MSW= 0,1) 28,58 — ns
7 Data setup time 15 — ns
8 CASx asserted before column address invalid 20 — ns
MD[12:0]
CASx
RASx
DWE
OE
D[15:0]
4
5
713
212
11
8
1
9
614
10
3
Row Col 1 Col 2 Col 3 Col n Col n+1