Motorola MC68VZ328 4.5.4 Power Control Register

4-14 MC68VZ328 User’s Manual 
Introduction to the Power Control Module
4.5.4 Power Control Register
The power control register (PCTLR) enables the power control module and det ermines whe n the CPUCLK
signal is applied to the CPU. The settings for each bit and field in the register are described in Table4-5.
PCTLR Power Control Register 0x(FF)FFF207
BIT 7654321BIT 0
PCEN WIDTH
TYPE rw rw rw rw rw rw
RESET 00011111
0x1F
Table 4-5. Power Control Register Description
Name Description Setting
PCEN
Bit 7 Power Control Enable—This bit controls the operation of the power control module. While
this bit is low, the CPU clock is on continu-
ously. When this bit is high, the pulse-width
comparator presents the clock to the CPU in
bursts or disables it. When this bit is high, a
masked interrupt can disable the power control
module.
0 = Power control is disabled (default).
1 = Power control is enabled.
Reserved
Bits 6–5 Reserved These bits are reserved and should remain set to 0.
WIDTH
Bits 4–0 Width—This field controls the width of the CPU clock bursts in increments of one
thirty-first. While this bit is set to 1 and the
PCM is enabled, the clock is applied to the
CPU in burst widths of one thirty-first (3 per-
cent). When the width field is 0x1F, the clock is
always on, and when it is 0, the clock is always
off. You can immediately wake it up again with-
out waiting for the PLL to reacquire lock. The
contents of this field are not affected by the
PCEN bit. When an interrupt disables the
power control module, these bits are not
changed.
00000 = 0/31 clock burst width.
00001 = 1/31 clock burst width.
00010 = 2/31 clock burst width.
.
.
.
11111 = 31/31 clock burst width.