7-18 MC68VZ328 User’s Manual
Programming Model
7.3.4 SDRAM Power-down Register

This register controls how the SDRAM and the MC68VZ328 operate during a power-down operat ion. Th e

bit position and values are shown in the following register display. The details about the register settings

are described in Table7-10.

SDPWDN SDRAM Power-down Register 0x(FF)FFFC06

BIT
15 14 13 1211 10 987654321
BIT
0
APEN PDEN PDTOUT[3:0]
TYPE rw rw rw rw rw rw
RESET 0 0 0 0 0 0 000000000 0
0x0000
Table 7-10. SDRAM Power-down Register Description
Name Description Settings
APEN
Bit 15 SDRAM Active Power-down Enable—The bit is set to
make the SDRAM Chip Enable signal go low immedia tely
when the DRAM controller is not sending a command, writ-
ing data, or reading data with the SDRAM.
0 = APEN disabled.
1 = APEN enabled.
PDEN
Bit 14 SDRAM Precharged Power-down Enable—The bit is set
to make the SDRAM Chip Enable signal go low when the
DRAM controller is not sending a command after t he
SDRAM is precharged for a certain time. The time depends
on the value in PDTOUT[3:0].
0 = PDEN disabled.
1 = PDEN enabled.
Reserved
Bits 13–12 Reserved These bits are reserved and
should be set to 0.
PDTOUT [3:0]
Bits 11–8 SDRAM Precharged Power-down Time Out—The bit is
set to make the SDRAM Chip Enable signal go low when a
time out occurs when the PDEN bit is set. Each binary unit
represents a maximum of 128 clocks. When in power-down
mode, SDRAM can be woken by a CPU or LCD access.
See the description.
Reserved
Bits 7–0 Reserved These bits are reserved and
should be set to 0.