Motorola MC68VZ328 , 14.3.3.1 Divider, 14.3.3.2 Non-Integer Prescaler

UART Operation
Universal Asynchronous Receiver/Transmitter 1 and 2 14-7
Figure 14-4. Baud Rate Generator Block Diagram
The baud rate generator’s master clock source can be the system clock (SYSCLK), or it c an be provided by
the UCLK pin (input mode). By setting the BAUD SRC bit of the corresponding UART baud control
(UBAUD) register to 1, an external clock can directly drive the baud rate generator. For synchronous
applications, the UCLK signal can be configured as an input or output for the 1x bit clock.
14.3.3.1 Divider
The divider is a 2n binary divider with eight taps—1, 2, 4, 8, 16, 32, 64, and 128. The selected tap is the
16x clock (CLK16) for the receiver. This clock is further divided by 16 to provi de a 50- per ce nt duty-cycle
1x clock (CLK1) to the transmitter. While the CLKM bit of the USTCNT register is high, CLK1 is directly
sourced by the CLK16 signal.
14.3.3.2 Non-Integer Prescaler
The non-integer prescaler is used to generate special, nonstandard baud frequencies. When IrDA mode is
enabled, zeros are transmitted as three-sixteenth bit-time pulses.
NOTE:
If the integer prescaler is used in IrDA operation , the baud rate will b e
determined by the integer prescaler. The non-inte ger pre scaler wil l then be
used for controlling the pulse width, but it must be less than or equal to
three-sixteenths of bit time.
For example, in IrDA mode, the non-integer prescaler provides a clock at 1.843200MHz
(115.200 kHz×16). This clock is used to generate transmit pulses, which are three-sixteenths of a
115.200 kHz bit time.
Table 14-1 on page14-8 contains the values to use for IrDA operation.
Integer
Non-Integer
Divider Divide
(Divide by 2n)by
16
Prescaler
Prescaler
0
1
0
1
0
1
PRE SEL
BAUD SRC
SYSCLK
UCLK IN
CLK16
CLK1
IRCLK
CLK SRC
0
1
Master Clock
PCLK
CLK MODE