Main
Page
Contents
About This Book
Chapter 1 Introduction
Chapter 2 Signal Descriptions
Chapter 3 Memory Map
Chapter 4 Clock Generation Module and Power Control Module
Chapter 5 System Control
Chapter 6 Chip-Select Logic
Chapter 7 DRAM Controller
Chapter 9 Interrupt Controller
Chapter 10 I/O Ports
Chapter 11 Real-Time Clock
Chapter 12 General-Purpose Timers
Chapter 13 Serial Peripheral Interface 1 and 2
Chapter 14 Universal Asynchronous Receiver/Transmitter 1 and 2
Chapter 15 Pulse-Width Modulator 1 and 2
Chapter 16 In-Circuit Emulation
Chapter 17 Bootstrap Mode
Chapter 18 Application Guide
Chapter 19 Electrical Characteristics
Chapter 20 Mechanical Data and Ordering Information
Index
Page
List of Figures
Page
Page
Page
List of Tables
Page
Page
Page
Page
Page
List of Examples
Page
About This Book
Audience
Organization
Page
Suggested Reading
Conventions
Definitions, Acronyms, and Abbreviations
Chapter 1 Introduction
1.1 Features of the MC68VZ328
Page
1.2 CPU
1.2.1 CPU Programming Model
1-6 MC68VZ328 Users Manual
CPU
1.2.2 Data and Address Mode Types
1.2.3 FLX68000 Instruction Set
Table 1-1. Address Modes
CPU
1.3 Modules of the MC68VZ328
1.3.1 Memory Controller
1.3.2 Clock Generation Module and Power Control Module
1.3.3 System Control
1.3.4 Chip-Select Logic
1.3.5 DRAM Controller
1.3.6 LCD Controller
1.3.7 Interrupt Controller
1.3.8 General-Purpose I/O (GPIO) Lines
1.3.9 Real-Time Clock
1.3.10 General-Purpose Timer
1.3.11 Serial Peripheral Interfaces (SPI)
1.3.12 Universal Asynchronous Receiver/Transmitter (UART) Modules
1.3.13 Pulse-Width Modulators (PWM)
1.3.14 In-Circuit Emulation Module
1.3.15 Bootstrap Mode
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Page
2-2 MC68VZ328 Users Manual
Signals Grouped by Function
Figure 2-1. Signals Grouped by Function
2.1 Signals Grouped by Function
Table 2-1 on page2-3 groups the MC68VZ328 signals according to their function.
Signals Grouped by Function
Table 2-1. Signal Function Groups
2.2 Power and Ground Signals
2.3 Clock and System Control Signals
2.4 Address Bus Signals
2.5 Data Bus Signals
2.6 Bus Control Signals
2.7 Interrupt Controller Signals
2.8 LCD Controller Signals
2.9 UART 1 and UART 2 Controller Signals
2.10 Timer Signals
2.11 Pulse-Width Modulator Signals
2.12 Serial Peripheral Interface 1 Signals
2.13 Serial Peripheral Interface 2 Signals
2.14 Chip-Select and EDO RAM Interface Signals
2.15 SDRAM Interface Signals
2.16 In-Circuit Emulation (ICE) Signals
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Chapter 3 Memory Map
Figure 3-1. MC68VZ328 System Memory Map
3-2 MC68VZ328 Users Manual
3.1 Programmers Memory Map
Table 3-1. Programmers Memory Map (Sorted by Address)
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3-6 MC68VZ328 Users Manual
3-8 MC68VZ328 Users Manual
Table 3-2. Programmers Memory Map (Sorted by Register Name)
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3-12 MC68VZ328 Users Manual
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Chapter 4 Clock Generation Module and Power Control Module
4.1 Introduction to the Clock Generation Module
4.2 CGM Operational Overview
4.3 Detailed CGM Clock Descriptions
4.3.1 CLK32 Clock Signal
Eqn. 4-1
4.3.2 PLLCLK Clock Signal
4.3.2.1 PLLCLK Initial Power-up Sequence
4.3.2.2 PLL Frequency Selection
Eqn. 4-2
4.3.2.3 PLLCLK Frequency Selection Programming Example
4.3.2.4 Programming Considerations When Changing Frequencies
4-8 MC68VZ328 Users Manual
4.4 CGM Programming Model
This section describes the two registers that enable and control the frequency of the CGM clocks.
4.4.1 PLL Control Register
PLLCR PLL Control Register 0xFFFFF200
Table 4-2. PLL Control Register Description
4.5 Introduction to the Power Control Module
4.5.1 Operating the PCM
4.5.1.1 Normal Mode
4.5.1.2 Burst Mode
4.5.1.3 Doze Mode
4.5.1.4 Sleep Mode
4.5.2 CGM Operation During Sleep Mode
4.5.3 Burst Mode Operation
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4-14 MC68VZ328 Users Manual
Introduction to the Power Control Module
4.5.4 Power Control Register
PCTLR Power Control Register 0x(FF)FFF207
Table 4-5. Power Control Register Description
Chapter 5 System Control
5.1 System Control Operation
5.1.1 Bus Monitors and Watchdog Timers
5-2 MC68VZ328 Users Manual
5.2 Programming Model
5.2.1 System Control Register
SCR System Control Register 0x(FF)FFF000
Table 5-1. System Control Register Description
Page
5-4 MC68VZ328 Users Manual
5.2.2 Peripheral Control Register
PCR Peripheral Control Register 0x(FF)FFF003
Table 5-2. Peripheral Control Register Description
5.2.3 ID Register
IDR ID Register 0x(FF)FFF004
Table 5-3. ID Register Description
5-6 MC68VZ328 Users Manual
5.2.4 I/O Drive Control Register
IODCR I/O Drive Control Register 0x(FF)FFF008
Table 5-4. I/O Drive Control Register Description
Chapter 6 Chip-Select Logic
6.1 Overview of the CSL
6.2 Chip-Select Operation
6.2.1 Memory Protection
6.2.2 Programmable Data Bus Size
6.2.3 Overlapping Chip-Select Registers
6.3 Programming Model
6.3.1 Chip-Select Group Base Address Registers
CSGBA Chip-Select Group A Base Address Register 0x(FF)FFF100
CSGBB Chip-Select Group B Base Address Register 0x(FF)FFF102
CSGBC Chip-Select Group C Base Address Register 0x(FF)FFF104
6.3.2 Chip-Select Upper Group Base Address Register
CSUGBA Chip-Select Upper Group Base Address Register 0 x(FF)FFF108
Table 6-5. Chip-Select Group D Base Address Register Description
Table 6-6. Chip-Select Upper Group Base Address Register Description
Table 6-6. Chip-Select Upper Group Base Address Register Description (Continued)
6.3.3 Chip-Select Registers
CSA Chip-Select Register A 0x(FF)FFF110
Table 6-7. Chip-Select Register A Description
Table 6-7. Chip-Select Register A Description (Continued)
6-10 MC68VZ328 Users Manual
CSB Chip-Select Register B 0x(FF)FFF112
Table 6-8. Chip-Select Register B Description
Table 6-8. Chip-Select Register B Description (Continued)
6-12 MC68VZ328 Users Manual
CSC Chip-Select Register C 0x(FF)FFF114
Table 6-9. Chip-Select Register C Description
Table 6-9. Chip-Select Register C Description (Continued)
6-14 MC68VZ328 Users Manual
CSD Chip-Select Register D 0x(FF)FFF116
Table 6-10. Chip-Select Register D Description
Table 6-10. Chip-Select Register D Description (Continued)
6.3.4 Emulation Chip-Select Register
EMUCS Emulation Chip-Select Register 0x(FF)FFF118
6.3.5 Chip-Select Control Register 1
CSCTRL1 Chip-Select Control Register 1 0x(FF)FFF10A
Table 6-12. Chip-Select Control Register 1 Description
6.3.6 Chip-Select Control Register 2
CSCTRL2 Chip-Select Control Register 2 0x(FF)FFF10C
Table 6-13. Chip-Select Control Register 2 Description
Table 6-12. Chip-Select Control Register 1 Description (Continued)
----------------------------------------=
6.3.7 Chip-Select Control Register 3
This register controls minor timing trims for static memory access.
CSCTRL3 Chip-Select Control Register 3 0x(FF)FFF150
Table 6-14. Chip-Select Control Register 3 Description
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Page
Chapter 7 DRAM Controller
7.1 Introduction to the DRAM Controller
7-2 MC68VZ328 Users Manual
Introduction to the DRAM Controller
Figure 7-1. DRAM Controller Block Diagram
7.2 DRAM Controller Operation
7.2.1 Address Multiplexing
7-4 MC68VZ328 Users Manual
Table 7-1. DRAM Address Multiplexing Options
Table 7-2. 16Mbit SDRAM256 (16-Bit) and 512 (8-Bit) Page Size
Table 7-3. 64Mbit SDRAM256 (16-Bit) and 512 (8-Bit) Page Size
7-6 MC68VZ328 Users Manual
Table 7-4. 128Mbit SDRAM512 (16-Bit) and 1024 (8-Bit) Page Size
Table 7-5. 256Mbit SDRAM512 (16-Bit) and 1024 (8-Bit) Page Size
7.2.2 DTACK Generation
7.2.3 Refresh Control
7.2.4 LCD Interface
7.2.5 8-Bit Mode
7.2.6 Low-Power Standby Mode
7-10 MC68VZ328 Users Manual
7.2.7 Data Retention During Reset
Figure 7-3. Data Retention for the Reset Cycle
7.2.8 Data Retention Sequence
7-12 MC68VZ328 Users Manual
7.3 Programming Model
This section describes the programming model for the DRAM controller.
7.3.1 DRAM Memory Configuration Register
DRAMMC DRAM Memory Configuration Register 0x(FF)FFFC00
Table 7-6. DRAM Memory Configuration Register Description
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7-14 MC68VZ328 Users Manual
7.3.2 DRAM Control Register
DRAMC DRAM Control Register 0x(FF)FFFC02
Table 7-7. DRAM Control Register Description
Table 7-7. DRAM Control Register Description (Continued)
7-16 MC68VZ328 Users Manual
7.3.3 SDRAM Control Register
SDCTRL SDRAM Control Register 0x(FF)FFFC04
Table 7-8. SDRAM Control Register Description
Table 7-9. SDRAM Bank Address Programming Examples
Table 7-8. SDRAM Control Register Description (Continued)
7.3.4 SDRAM Power-down Register
SDPWDN SDRAM Power-down Register 0x(FF)FFFC06
Table 7-10. SDRAM Power-down Register Description
Chapter 8 LCD Controller
8.1 LCD Controller Features
8.2 LCD Controller Operation
8.2.1 Connecting the LCD Controller to an LCD Panel
8.2.1.1 Panel Interface Timing
8-4 MC68VZ328 Users Manual
LCD Controller Operation
Figure 8-2. LCD Interface Timing for 4-, 2-, and 1-Bit Data Widths
8.2.2 Controlling the Display
8.2.2.1 Format of the LCD Screen
8.2.2.2 Format of the Cursor
8.2.2.3 Mapping the Display Data
8.2.2.4 Generating Grayscale Tones
Page
8.2.3 Using Low-Power Mode
8.2.4 Using the DMA Controller
8.2.4.1 Bus Bandwidth Calculation Example
8.2.5 Self-Refresh Mode
8.2.5.1 Entering Self-Refresh Mode
8.2.5.2 Canceling Self-Refresh Mode
8-10 MC68VZ328 Users Manual
8.3 Programming Model
and should be set to 0.
8.3.1 LCD Screen Starting Address Register
LSSA LCD Screen Starting Address Register 0x(FF)FFFA00
Table 8-2. LCD Screen Starting Address Register Description
8.3.2 LCD Virtual Page Width Register
LXMAX LCD Screen Width Register 0x(FF)FFFA08
LVPW LCD Virtual Page Widt h Register 0x(FF)FFFA05
8.3.3 LCD Screen Width Register
Table 8-3. LCD Virtual Page Width Register Description
8.3.4 LCD Screen Height Register
LCXP LCD Cursor X Position Register 0x(FF)FFFA18
LYMAX LCD Screen Height Register 0x(FF)FFFA0A
8.3.5 LCD Cursor X Position Register
Table 8-5. LCD Screen Height Register Description
8.3.6 LCD Cursor Y Position Register
LCYP LCD Cursor Y Position Register 0x(FF)FFFA1A
Table 8-7. LCD Cursor Y Position Register Description
Table 8-6. LCD Cursor X Position Register Description (Continued)
8.3.7 LCD Cursor Width and Height Register
LCWCH LCD Cursor Width and Height Register 0x(FF)FFFA1C
8.3.8 LCD Blink Control Register
LBLKC LCD Blink Control Register 0x(FF)FFFA1F
LPICF LCD Panel Interface Configuration Register 0x(FF)FFFA20
8.3.9 LCD Panel Interface Configuration Register
Table 8-9. LCD Blink Control Register Description
Table 8-10. LCD Panel Interface Configuration Register Description
8-16 MC68VZ328 Users Manual
8.3.10 LCD Polarity Configuration Register
LPOLCF LCD Polarity Configuration Register 0x(FF)FFFA21
8.3.11 LACD Rate Control Register
Table 8-11. LCD Polarity Configuration Register Description
LACDRC LACD Rate Control Register 0x(FF)FFFA23
8.3.12 LCD Pixel Clock Divider Register
Table 8-12. LACD Rate Control Register Description
Table 8-13. LCD Pixel Clock Divider Register Description
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8.3.13 LCD Clocking Control Register
LRRA LCD Refresh Rate Adjustment Register 0x(FF)FFFA28
LCKCON LCD Clocking Control Register 0x(FF)FFFA27
8.3.14 LCD Refresh Rate Adjustment Register
Table 8-14. LCD Clocking Control Register Description
8.3.15 LCD Panning Offset Register
LPOSR LCD Panning Offset Register 0x(FF)FFFA2D
8.3.16 LCD Frame Rate Control Modulation Register
Table 8-16. LCD Panning Offset Register Description
Table 8-15. LCD Refresh Rate Adjustment Register Description (Continued)
8.3.17 LCD Gray Palette Mapping Register
PWMR PWM Contrast Control Register 0x(FF)FFFA36
LGPMR LCD Gray Palette Mapping Register 0x(FF)FFFA33
8.3.18 PWM Contrast Control Register
Table 8-17. LCD Gray Palette Mapping Register Description
8.3.19 Refresh Mode Control Register
RMCR Refresh Mode Control Register 0x(FF)FFFA38
Table 8-19. Refresh Mode Control Register Description
Table 8-18. PWM Contrast Control Register Description (Continued)
8.3.20 DMA Control Register
8.4 Programming Example
Chapter 9 Interrupt Controller
9.1 Interrupt Processing
9.2 Exception Vectors
9.3 Reset
9.3.1 Operation Mode Selection During Reset
9.3.2 Data Bus Width for Boot Device Operation
9.4 Interrupt Controller Operation
9.4.1 Interrupt Priority Processing
9.4.2 Interrupt Vectors
9.5 Vector Generation
9.6 Programming Model
9.6.1 Interrupt Vector Register
IVR Interrupt Vector Register 0x(FF)FFF300
9-8 MC68VZ328 Users Manual
9.6.2 Interrupt Control Register
ICR Interrupt Control Register 0x(FF)FFF302
Table 9-4. Interrupt Control Register Description
Table 9-4. Interrupt Control Register Description (Continued)
9.6.3 Interrupt Mask Register
IMR Interrupt Mask Register 0x(FF)FFF304
Table 9-5. Interrupt Mask Register Description
Table 9-5. Interrupt Mask Register Description (Continued)
9.6.4 Interrupt Status Register
ISR Interrupt Status Register 0xFFFFF30C
Table 9-6. Interrupt Status Register Description
Table 9-6. Interrupt Status Register Description (Continued)
9-14 MC68VZ328 Users Manual
Table 9-6. Interrupt Status Register Description (Continued)
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9-16 MC68VZ328 Users Manual
9.6.5 Interrupt Pending Register
IPR Interrupt Pending Register 0x(FF)FFF310
Table 9-7. Interrupt Pending Register Description
Table 9-7. Interrupt Pending Register Description (Continued)
9-18 MC68VZ328 Users Manual
Table 9-7. Interrupt Pending Register Description (Continued)
9.6.6 Interrupt Level Register
ILCR Interrupt Level Register 0x(FF)FFF314
9.7 Keyboard Interrupts
9.8 Pen Interrupts
Chapter 10 I/O Ports
10.1 Port Configuration
10.2 Status of I/O Ports During Reset
10.2.1 Warm Reset
10.2.2 Power-up Reset
10.2.3 Summary of Port Behavior During Reset
10.3 I/O Port Operation
10.3.1 Data Flow from the I/O Module
10.3.2 Data Flow to the I/O Module
10.3.3 Operating a Port as GPIO
10.3.4 Port Pull-up and Pull-down Resistors
10.4 Programming Model
10.4.1 Port A Registers
10.4.1.1 Port A Direction Register
PADATA Port A Data Register 0x(FF)FFF401
PADIR Port A Direction Register 0x(FF)FFF400
10.4.2 Port B Registers
10.4.2.1 Port B Direction Register
PBDIR Port B Direction Register 0x(FF)FFF408
10.4.2.2 Port B Data Register
PBDATA Port B Data Register 0x(FF)FFF409
10.4.2.3 Port B Dedicated I/O Functions
10.4.2.4 Port B Pull-up Enable Register
PBPUEN Port B Pull-up Enable Register 0x(FF)FFF40A
10.4.2.5 Port B Select Register
PBSEL Port B Select Register 0x(FF)FFF40B
10.4.3 Port C Registers
10.4.3.1 Port C Direction Register
PCDIR Port C Direction Register 0x(FF)FFF410
10.4.3.2 Port C Data Register
PCDATA Port C Data Register 0x(FF)FFF411
10.4.3.3 Port C Dedicated I/O Functions
10.4.3.5 Port C Select Register
PCSEL Port C Select Register 0x(FF)FFF413
Table 10-16. Port C Select Register Description
10.4.4 Port D Operation
10.4.5 Port D Registers
10.4.5.1 Port D Direction Register
PDDIR Port D Direction Register 0x(FF)FFF418
10.4.5.2 Port D Data Register
PDDATA Port D Data Register 0x(FF)FFF419
10.4.5.3 Port D Interrupt Options
10.4.5.4 Port D Pull-up Enable Register
PDPUEN Port D Pull-up Enable Register 0x(FF)FFF41A
10.4.5.5 Port D Select Register
PDPOL Port D Polarity Register 0x(FF)FFF41C
10.4.5.7 Port D Interrupt Request Enable Register
PDIRQEN Port D Interrupt Request Enable Register 0x(FF)FFF41D
10.4.5.8 Port D Keyboard Enable Register
PDKBEN Port D Keyboard Enable Register 0x(FF)FFF41E
10.4.5.9 Port D Interrupt Request Edge Register
10.4.6 Port E Registers
10.4.6.1 Port E Direction Register
10.4.6.2 Port E Data Register
PEDATA Port E Data Register 0x(FF)FFF421
10.4.6.3 Port E Dedicated I/O Functions
10.4.6.4 Port E Pull-up Enable Register
PESEL Port E Select Register 0x(FF)FFF423
10.4.7 Port F Registers
10.4.7.1 Port F Direction Register
PFDIR Port F Direction Register 0x(FF)FFF428
10.4.7.2 Port F Data Register
PFDATA Port F Data Register 0x(FF)FFF429
10.4.7.3 Port F Dedicated I/O Functions
10.4.7.4 Port F Pull-up/Pull-down Enable Register
PFSEL Port F Select Register 0x(FF)FFF42B
PFPUEN Port F Pull-up/Pull-down Enable Register 0x(FF)FFF42A
10.4.7.5 Port F Select Register
10.4.8 Port G Registers
10.4.8.1 Port G Direction Register
PGDIR Port G Direction Register 0x(FF)FFF430
10.4.8.2 Port G Data Register
PGDATA Port G Data Register 0x(FF)FFF431
10.4.8.4 Port G Operational Considerations
10.4.8.5 Port G Pull-up Enable Register
PGPUEN Port G Pull-up Enable Register 0x(FF)FFF432
10.4.8.6 Port G Select Register
PGSEL Port G Select Register 0x(FF)FFF433
10.4.9 Port J Registers
10.4.9.1 Port J Direction Register
10.4.9.2 Port J Data Register
PJDATA Port J Data Register 0x(FF)FFF439
10.4.9.3 Port J Dedicated I/O Functions
10.4.9.4 Port J Pull-up Enable Register
PJPUEN Port J Pull-up Enable Register 0x(FF)FFF43A
10.4.10 Port K Registers
10.4.10.1 Port K Direction Register
PKDIR Port K Direction Register 0x(FF)FFF440
10.4.10.2 Port K Data Register
PKDATA Port K Data Register 0x(FF)FFF441
10.4.10.4 Port K Pull-up/Pull-down Enable Register
PKPUEN Port K Pull-up/Pull-down Enable Register 0x(FF)FFF442
PKSEL Port K Select Register 0x(FF)FFF443
10.4.10.5 Port K Select Register
10.4.11 Port M Registers
10.4.11.1 Port M Direction Register
PMDIR Port M Direction Register 0x(FF)FFF448
10.4.11.2 Port M Data Register
PMDATA Port M Data Register 0x(FF)FFF449
10.4.11.3 Port M Dedicated I/O Functions
PMPUEN Port M Pull-up/Pull-down Enable Register 0x(FF)FFF44A
10.4.11.4 Port M Pull-up/Pull-down Enable Register
10.4.11.5 Port M Select Register
PMSEL Port M Select Register 0x(FF)FFF44B
Table 10-55. Port M Select Register Description
Chapter 11 Real-Time Clock
Figure 11-1. Real-Time Clock Module Simplified Block Diagram
11.1 RTC Overview
11.1.1 Prescaler
11.1.2 Time-of-Day Counter
11.1.3 Alarm
11.1.4 Watchdog Timer
11.1.5 Real-Time Interrupt Timer
11.1.6 Minute Stopwatch
11.1.6.1 Minute Stopwatch Application Example
11.2 Programming Model
11.2.1 RTC Time Register
RTCTIME RTC Hours, Minutes, and Seconds Register 0x(FF)FFFB00
Table 11-2. RTC Hours, Minutes, and Seconds Register Description
11.2.2 RTC Day Count Register
DAYR RTC Day Counter Register 0x(ff)FFFB1A
11.2.3 RTC Alarm Register
RTCALRM RTC Alarm Register 0x(ff)FFFB04
Table 11-4. RTC Alarm Register Description
11-8 MC68VZ328 Users Manual
11.2.4 RTC Day Alarm Register
DAYALRM RTC Day Alarm Register 0x(ff)FFFB1C
Table 11-5. RTC Day Alarm Register Description
11.2.5 Watchdog Timer Register
WATCHDOG Watchdog Timer Register 0x(ff)FFFB0A
Table 11-6. Watchdog Timer Register Description
11.2.6 RTC Control Register
RTCCTL RTC Control Register 0x(ff)FFFB0C
11.2.7 RTC Interrupt Status Register
RTCISR RTC Interrupt Status Register 0x(ff)FFFB0E
Table 11-8. RTC Interrupt Status Register Description
11.2.8 RTC Interrupt Enable Register
Table 11-9. Real-Time Interrupt Frequency Settings
Table 11-8. RTC Interrupt Status Register Description (Continued)
RTCIENR RTC Interrupt Enable Register 0x(ff)FFFB10
Table 11-10. RTC Interrupt Enable Register Description
11.2.9 Stopwatch Minutes Register
STPWCH Stopwatch Minutes Register 0x(FF)FFFB12
Table 11-11. Stopwatch Minutes Register Description
Table 11-10. RTC Interrupt Enable Register Description (Continued)
Chapter 12 General-Purpose Timers
12.1 GP Timer Overview
12.1.1 Clock Source and Prescaler
12.1.2 Timer Events and Modes of Operation
12.1.2.1 Restart Mode
12.1.2.2 Free-Running Mode
12.1.3 Timer Capture Register
12.1.4 TOUT/TIN/PB6 Pin
12.1.5 Cascaded Timers
12.1.5.1 Compare and Capture Using Cascaded Timers
Page
12.2 Programming Model
12.2.1 Timer Control Registers 1 and 2
TCTL2 Timer Control Register 2 0x(FF)FFF610
TCTL1 Timer Control Register 1 0x(FF)FFF600
Table 12-2. Timer Control Register Description (Continued)
12.2.2 Timer Prescaler Registers 1 and 2
TPRER2 Timer Prescaler Register 2 0x(FF)FFF612
TPRER1 Timer Prescaler Register 1 0x(FF)FFF602
Table 12-3. Timer Prescaler Register Description
12.2.3 Timer Compare Registers 1 and 2
TCMP2 Timer Compare Register 2 0x(FF)FFF614
TCMP1 Timer Compare Register 1 0x(FF)FFF604
Table 12-4. Timer Compare Register Description
12-10 MC68VZ328 Users Manual
12.2.4 Timer Capture Registers 1 and 2
TCR2 Timer Capture Register 2 0x(FF)FFF616
TCR1 Timer Capture Register 1 0x(FF)FFF606
Table 12-5. Timer Capture Register Description
12.2.5 Timer Counter Registers 1 and 2
TCN2 Timer Counter Register 2 0x(FF)FFF618
TCN1 Timer Counter Register 1 0x(FF)FFF608
Table 12-6. Timer Counter Register Description
12-12 MC68VZ328 Users Manual
12.2.6 Timer Status Registers 1 and 2
TSTAT2 Timer Status Register 2 0x(FF)FFF61A
TSTAT1 Timer Status Register 1 0x(FF)FFF60A
Table 12-7. Timer Status Register Description
Chapter 13 Serial Peripheral Interface 1 and 2
13.1 SPI 1 Overview
13.2 SPI 1 Operation
13.2.1 Using SPI 1 as Master
13.2.2 Using SPI 1 as Slave
13.2.3 SPI 1 Phase and Polarity Configurations
13.2.4 SPI 1 Signals
13.3 SPI 1 Programming Model
13.3.1 SPI 1 Receive Data Register
SPIRXD SPI 1 Receive Data Register 0x(FF)FFF700
13.3.2 SPI 1 Transmit Data Register
SPITXD SPI 1 Transmit Data Register 0x(FF)FFF7 02
13-6 MC68VZ328 Users Manual
13.3.3 SPI 1 Control/Status Register
SPICONT1 SPI 1 Control/Status Register 0x(FF)FFF704
Table 13-3. SPI 1 Control/Status Register Description
Table 13-3. SPI 1 Control/Status Register Description (Continued)
13-8 MC68VZ328 Users Manual
13.3.4 SPI 1 Interrupt Control/Status Register
SPIINTCS SPI 1 Interrupt Control/Status Register 0x(FF)FFF706
Table 13-4. SPI 1 Interrupt Control/Status Register Description
Table 13-4. SPI 1 Interrupt Control/Status Register Description (Continued)
13-10 MC68VZ328 Users Manual
13.3.5 SPI 1 Test Register
SPITEST SPI 1 Test Register 0x(FF)FFF708
13.3.6 SPI 1 Sample Period Control Register
Table 13-5. SPI 1 Test Register Description
SPI 2 Overview
13.4 SPI 2 Overview
Figure 13-3. SPI 2 Block Diagram
Table 13-6. SPI 1 Sample Period Control Register Description
13.5 SPI 2 Operation
13.5.1 SPI 2 Phase and Polarity Configurations
13.5.2 SPI 2 Signals
13.6 SPI 2 Programming Model
13.6.1 SPI 2 Data Register
SPIDATA2 SPI 2 Data Register 0x(FF)FFF800
13.6.2 SPI 2 Data Register Timing
SPI 2 Programming Model
13.6.3 SPI 2 Control/Status Register
SPICONT2 SPI 2 Control/Status Register 0x(FF)FFF802
Table 13-8. SPI 2 Control/Status Register Description
13-16 MC68VZ328 Users Manual
SPI 2 Programming Model
Table 13-8. SPI 2 Control/Status Register Description (Continued)
Chapter 14 Universal Asynchronous Receiver/Transmitter 1 and 2
14.1 Introduction to the UARTs
14.2 Serial Operation
14.2.1 NRZ Mode
14.2.2 IrDA Mode
14.2.3 Serial Interface Signals
14.3 UART Operation
14.3.1 Transmitter Operation
14.3.1.1 TxFIFO Buffer Operation
14.3.1.2 CTS Signal Operation
14.3.2 Receiver Operation
14.3.2.1 Rx FIFO Buffer Operation
14.3.3 Baud Rate Generator Operation
14.3.3.1 Divider
14.3.3.2 Non-Integer Prescaler
Page
UART Operation
14.3.3.3 Integer Prescaler
14-10 MC68VZ328 Users Manual
14.4 Programming Model
14.4.1 UART 1 Status/Control Register
USTCNT1 UART 1 Status/Control Register 0x(FF)FFF900
Table 14-4. UART 1 Status/Control Register Description
Table 14-4. UART 1 Status/Control Register Description (Continued)
14.4.2 UART 1 Baud Control Register
UBAUD1 UART 1 Baud Control Register 0x(FF)FFF902
Table 14-5. UART 1 Baud Control Register Description
14.4.3 UART 1 Receiver Register
URX1 UART 1 Receiver Register 0x(FF)FFF904
Table 14-6. UART 1 Receiver Register Description
14-14 MC68VZ328 Users Manual
14.4.4 UART 1 Transmitter Register
UTX1 UART 1 Transmitter Register 0x(FF)FFF906
Table 14-7. UART 1 Transmitter Register Description
Table 14-6. UART 1 Receiver Register Description (Continued)
Table 14-7. UART 1 Transmitter Register Description (Continued)
14.4.5 UART 1 Miscellaneous Register
UMISC1 UART 1 Miscellaneous Register 0x(FF)FFF908
Table14-8. UART 1 Miscellaneous Register Description
Table 14-8. UART 1 Miscellaneous Register Description (Continued)
14-18 MC68VZ328 Users Manual
14.4.6 UART 1 Non-Integer Prescaler Register
NIPR1 UART 1 Non-Integer Prescaler Register 0x(FF)FFF90A
Table 14-9. UART 1 Non-Integer Prescaler Register Description
14.4.7 Non-Integer Prescaler Programming Example
14-20 MC68VZ328 Users Manual
14.4.8 UART 2 Status/Control Register
USTCNT2 UART 2 Status/Control Register 0x(FF)FFF910
Table 14-10. UART 2 Status/Control Register Description
Table 14-10. UART 2 Status/Control Register Description (Continued)
14-22 MC68VZ328 Users Manual
14.4.9 UART 2 Baud Control Register
UBAUD2 UART 2 Baud Control Register 0x(FF)FFF912
Table 14-11. UART 2 Baud Control Register Description
14.4.10 UART 2 Receiver Register
URX2 UART 2 Receiver Register 0x(FF)FFF914
Table 14-12. UART 2 Receiver Register Description
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14.4.11 UART 2 Transmitter Register
UTX2 UART 2 Transmitter Register 0x(FF)FFF916
Table 14-13. UART 2 Transmitter Register Description
Table 14-12. UART 2 Receiver Register Description (Continued)
Table 14-13. UART 2 Transmitter Register Description (Continued)
14.4.12 UART 2 Miscellaneous Register
UMISC2 UART 2 Miscellaneous Register 0x(FF)FFF918
Table14-14. UART 2 Miscellaneous Register Description
Table 14-14. UART 2 Miscellaneous Register Description (Continued)
14-28 MC68VZ328 Users Manual
14.4.13 UART 2 Non-Integer Prescaler Register
NIPR2 UART 2 Non-Integer Prescaler Register 0x(FF)FFF91A
Table 14-15. UART 2 Non-Integer Prescaler Register Description
14.4.14 FIFO Level Marker Interrupt Register
HMARK FIFO Level Marker Interrupt Register 0x(FF)FFF91C
Table 14-16. FIFO Level Marker Interrupt Register Description
14-30 MC68VZ328 Users Manual
Table 14-17. FIFO Level Marker Settings
Chapter 15 Pulse-Width Modulator 1 and 2
15.1 Introduction to PWM Operation
15.1.1 PWM Clock Signals
15.2 PWM 1
15.3 PWM Operation
15.3.1 Playback Mode
15.3.1.1 Tone Mode
15.3.1.2 D/A Mode
15-4 MC68VZ328 Users Manual
15.4 Programming Model
This section contains programming information about both PWM 1 and PWM 2.
15.4.1 PWM 1 Control Register
PWMC1 PWM 1 Control Register 0x(FF)FFF500
Table 15-1. PWM 1 Control Register Description
15.4.2 PWM 1 Sample Register
PWMS1 PWM 1 Sample Re gister 0x(FF)FFF502
15.4.3 PWM 1 Period Register
PWMCNT1 PWM 1 Counter Register 0x(FF)FFF505
Eqn. 15-1
PWMP1 PWM 1 Period Register 0x(FF)FFF504
15.4.4 PWM 1 Counter Register
15.5 PWM 2
Figure 15-4. PWM 2 Block Diagram
15.5.1 PWM 2 Control Register
PWMC2 PWM 2 Control Register 0x(FF)FFF510
Table 15-5. PWM 2 Control Register Description
15.5.2 PWM 2 Period Register
PWMP2 PWM 2 Period Register 0x(FF)FFF512
Table 15-6. PWM 2 Period Register Description
Table 15-5. PWM 2 Control Register Description (Continued)
15-10 MC68VZ328 Users Manual
15.5.3 PWM 2 Pulse Width Register
PWMCNT2 PWM 2 Counter Register 0x(FF)FFF516
PWMW2 PWM 2 Pulse Width Control Register 0x(FF)FFF514
15.5.4 PWM 2 Counter Register
Table 15-7. PWM 2 Pulse Width Control Register Description
Chapter 16 In-Circuit Emulation
16.1 ICE Operation
16.1.1 Entering Emulation Mode
16.1.2 Detecting Breakpoints
16.1.2.1 Execution Breakpoints vs. Bus Breakpoints
16.1.3 Using the Signal Decoder
16.1.4 Using the Interrupt Gate Module
16.1.5 Using the A-Line Insertion Unit
16.2 Programming Model
16.2.1 In-Circuit Emulation Module Address Compare and Mask Registers
ICEMACR ICE Module Address Compare Register 0x(FF)FFFFFD00
ICEMAMR ICE Module Address Mask Register 0x (FF)FFFFFD04
Table 16-1. ICE Module Address Compare and Mask Registers Description
16.2.2 In-Circuit Emulation Module Control Compare and Mask Register
ICEMCCR ICE Module Control Compare Register 0x(FF)FFFFFD08
ICEMCMR ICE Control Mask Register 0x(FF)FFFFFD0A
Page
16-8 MC68VZ328 Users Manual
16.2.3 In-Circuit Emulation Module Control Register
ICEMCR ICE Module Control Register 0x(FF)FFFFFD0C
Table 16-4. ICE Module Control Register Description
Page
16.2.4 In-Circuit Emulation Module Status Register
ICEMSR ICE Module Status Register 0x(FF)FFFFFD0E
16.3 Typical Design Programming Example
Typical Design Programming Example
Figure 16-2. Typical Emulator Design Example
16.3.1 Host Interface
16.3.2 Dedicated Debug Monitor Memory
16.4 Plug-in Emulator Design Example
Page
16-14 MC68VZ328 Users Manual
Application Development Design Example
16.5 Application Development Design Example
Figure 16-4. Application Development System Design Example
Chapter 17 Bootstrap Mode
17.1 Bootstrap Mode Operation
17.1.1 Entering Bootstrap Mode
17.1.2 Bootstrap Record Format
17.1.2.1 Data B-Record Format
17.1.2.2 Execution B-Record Format
17.1.3 Setting Up the RS-232 Terminal
17.1.4 Changing the Speed of Communication
17.1.5 System Initialization Programming Example
17.1.6 Application Programming Example
17.1.7 Example of Instruction Buffer Usage
17.2 Bootloader Flowchart
Bootloader Flowchart
Figure 17-2. Bootloader Program Operation
17.3 Special Notes
Chapter 18 Application Guide
18.1 Design Checklist
18.1.1 Determining the Chip ID and Version
18.1.2 8-Bit Bus Width Issues
18.1.3 Clock and Layout Considerations
18.1.4 Bus and I/O Considerations
Chapter 19 Electrical Characteristics
19.1 Maximum Ratings
19-2 MC68VZ328 Users Manual
19.2 DC Electrical Characteristics
Table 19-2 contains both maximum and minimum DC characteristics of the MC68VZ328.
19.3 AC Electrical Characteristics
19.3.1 CLKO Reference to Chip-Select Signals Timing
Table 19-2. Maximum and Minimum DC Characteristics
19.3.2 Chip-Select Read Cycle Timing
Table 19-3. CLKO Reference to Chip-Select Signals Timing Parameters
19-4 MC68VZ328 Users Manual
19.3.3 Chip-Select Write Cycle Timing
Figure 19-3. Chip-Select Write Cycle Timing Diagram
Table 19-4. Chip-Select Read Cycle Timing Parameters (Continued)
19-6 MC68VZ328 Users Manual
19.3.4 Chip-Select Flash Write Cycle Timing
Table 19-5. Chip-Select Write Cycle Timing Parameters
Page
19.3.5 Chip-Select Timing Trim
19.3.6 DRAM Read Cycle 16-Bit Access (CPU Bus Master)
Page
19-10 MC68VZ328 Users Manual
19.3.7 DRAM Write Cycle 16-Bit Access (CPU Bus Master)
Figure 19-7. DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Diagram
Table 19-8. DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Parameters (Continued)
19.3.8 DRAM Hidden Refresh Cycle (Normal Mode)
Table 19-9. DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Parameters
19-12 MC68VZ328 Users Manual
Figure 19-8. DRAM Hidden Refresh Cycle (Normal Mode) Timing Diagram
19.3.9 DRAM Hidden Refresh Cycle (Low-Power Mode)
Figure 19-9. DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Diagram
Table 19-10. DRAM Hidden Refresh Cycle (Normal Mode) Timing Parameters
19.3.10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access (1 Wait State)
Figure 19-10. LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Diagram
Table 19-11. DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Parameters
19-14 MC68VZ328 Users Manual
19.3.11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)
Figure 19-11. LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master) Timing Diagram
Table 19-12. LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Parameters
Table 19-13. LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master) Timing Parameters
19-16 MC68VZ328 Users Manual
19.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
19.3.13 LCD Controller Timing
Figure 19-13. LCD Controller Timing Diagram (Normal Mode)
Page
19.3.14 Page-Miss SDRAM CPU Read Cycle (CAS
Figure 19-15. Page-Miss SDRAM CPU Read Cycle Timing Diagram
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19.3.15 Page-Hit SDRAM CPU Read Cycle (CAS Latency = 1)
Figure 19-16. Page-Hit SDRAM CPU Read Cycle Timing Diagram
19.3.16 Page-Hit CPU Read Cycle for 8-Bit SDRAM (CAS
Figure 19-17. Page-Hit CPU Read Cycle for 8-Bit SDRAM Timing Diagram
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19.3.17 Page-Miss SDRAM CPU Write Cycle (CAS
Figure 19-18. Page-Miss SDRAM CPU Write Cycle Timing Diagram
19.3.18 Page-Hit SDRAM CPU Write Cycle (CAS Latency = 1)
Figure 19-19. Page-Hit SDRAM CPU Write Cycle Timing Diagram
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19.3.19 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM (CAS
Figure 19-20. Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM Timing Diagram
Figure 19-21. Page-Hit CPU Read Cycle in Power-down Mode Timing Diagram
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Figure 19-22. Exit Self-Refresh Due to CPU Read Cycle Timing Diagram
19.3.22 Enter Self-Refresh Due to No Activity for 64 Clocks (Bit RM of DRAM Control Register = 1)
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19.3.23 Page-Miss at Starting of LCD DMA for SDRAM (CAS
Figure 19-24. Page-Miss at Starting of LCD DMA for SDRAM Timing Diagram
19.3.24 Page-Miss at Start and in Middle of LCD DMA (CAS
Figure 19-25. Page-Miss at Start and in Middle of LCD DMA Timing Diagram
19-30 MC68VZ328 Users Manual
19.3.25 Page-Hit LCD DMA Cycle for SDRAM (CAS
Figure 19-26. Page-Hit LCD DMA Cycle for SDRAM Timing Diagram
Table 19-16. Timing Parameters for Figure19-15 Through Figure 19-26
19.3.26 SPI 1 and SPI 2 Generic Timing
19.3.27 SPI 1 Master Using DATA_READY Edge Trigger
19.3.28 SPI 1 Master Using DATA_READY Level Trigger
19.3.29 SPI 1 Master Dont Care DATA_READY
19.3.30 SPI 1 Slave FIFO Advanced by Bit Count
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19.3.31 SPI 1 Slave FIFO Advanced by SS Rising Edge
19.3.32 Normal Mode Timing
19.3.33 Emulation Mode Timing
19.3.34 Bootstrap Mode Timing
Chapter 20 Mechanical Data and Ordering Information
This chapter provides mechanical data, including illustrations, and ordering information.
20.1 Ordering Information
Table 20-1. MC68VZ328 Ordering Information
20-2 MC68VZ328 Users Manual
20.2 TQFP Pin Assignments
Figure 20-1 provides a top view of TQFP pin assignments.
Figure 20-1. MC68VZ328 TQFP Pin AssignmentsTop View
MC68VZ328 Top View
TQFP Package Dimensions
20.3 TQFP Package Dimensions
Figure 20-2. MC68VZ328 TQFP Mechanical Drawing
20-4 MC68VZ328 Users Manual
MAPBGA Pin Assignments
Top View
20.4 MAPBGA Pin Assignments
Figure 20-3 provides a top view of the MAPBGA pin assignments.
Figure 20-3. MC68VZ328 MAPBGA Pin AssignmentsTop View
1 A
23456789101112 B C D E F G H J K L M
20.5 MAPBGA Package Dimensions
Figure 20-4. MC68VZ328 MAPBGA Mechanical Drawing
CASE 1242A-03 ISSUE B
Page
Index
Numerics
A
B
C
Page
D
E
F
G
H
I
Page
K
L
M
N
O
P
Page
Page
Q
R
S
Page
T
U
V
W
X
Y
