Motorola MC68VZ328 6.3.2 Chip-Select Upper Group Base Address Register

6-6 MC68VZ328 User’s Manual 
Programming Model
CSGBD Chip-Select Group D Base Address Register 0x(FF)FFF106
6.3.2 Chip-Select Upper Group Base Address Register
The default setting for chip-select decoding limits addressing to A28. When the ful l addr ess deco de en able
(UGEN) bit is set, it allows full address decoding. Full address decoding is enabled for all four of the
chip-select registers by the UGEN bit in the chip-select upper gr oup bas e addres s re giste r (CSUGBA). The
bit value of the MSB for each of the four chip-select registers can be written into each of the four MSB
fields in this register. The settings for this register are shown in Table6-6.
CSUGBA Chip-Select Upper Group Base Address Register 0 x(FF)FFF108
BIT
15 1413121110987654321
BIT
0
GB
D2
8
GB
D2
7
GB
D2
6
GB
D2
5
GB
D2
4
GB
D2
3
GB
D2
2
GB
D2
1
GB
D2
0
GB
D1
9
GB
D1
8
GB
D1
7
GB
D1
6
GB
D1
5
GB
D1
4
TYPE rw rw rw rw rw rw rw rw r w rw rw rw rw rw rw
RESET 0000000000000000
0x0000
Table 6-5. Chip-Select Group D Base Address Register Description
Name Description Setting
GBDx
Bits 15–1Group D Base Address—These bits select the high-order bits (28–14) of the starting
address for the chip-select range.
The chip-select base address must be set
according to the size of the corresponding
chip-select signals of the group.
Reserved
Bit 0 Reserved This bit is reserved and should be set to 0.
BIT
15 1413121110987654321
BIT
0
UG
EN AGBA[31:29] BGBA[31:29] CGBA[31:29] DGBA[31:29]
TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET 0000000000000000
0x0000
Table 6-6. Chip-Select Upper Group Base Address Register Description
Name Description Setting
UGEN
Bit 15 Full Address Decode Enable—This bit enables full address range decoding for all
chip-select registers.
0 = Ignores A31, A30, and A29.
1 = Decoding includes A31, A30, and A29.
AGBA[31:29]
Bits 14–12 MSB for Chip-Select A—The upper most sig- nificant bits for chip-select group A base
address. The value will be ignored if UGEN is
disabled.
Enter value for bits 31–29 of chip-sele ct regis-
ter A.