MVME2603/2604 Base Board Block Diagram | Motorola MVME2600 specification

1

Hardware Preparation and Installation

CLOCK

DEBUG CONNECTOR

MEMORY EXPANSION CONNECTORS

GENERATOR

BUS

L2 CACHE

256K

PROCESSOR

FLASH

FLASH

1MB

4MB or 8MB

PROCESSOR

SYSTEM

MPC603/604

MPC604

REGISTERS

PHB & MPIC

MEMORY CONTROLLER

66MHz

RAVEN ASIC

FALCON CHIPSET

PMCBIT-64 SLOT

EXPANSIONPCI

33MHz 32/64-BIT PCI LOCAL BUS

				PIB	ETHERNET	SCSI
			W83C553		DEC21140	53C825A
& LED		ISA
FLOPPY		REGISTERS			AUI/10BT/100BTX
			ISA BUS	RTC/NVRAM/WD
			ISA BUS	MK48T59
				MK48T59
KBD
MOUSE		SUPER I/O		ESCC	CIO
			PC87308	85230	Z8536

PMC FRONT I/O SLOT		PARALLEL	712/761 P2 I/O OPTIONS
PMC FRONT I/O SLOT	FRONTPANEL	PARALLEL	SERIAL

VME BRIDGE

UNIVERSE

BUFFERS

VME P2		VME P1

Figure 1-1. MVME2603/2604 Base Board Block Diagram

1-2	Computer Group Literature Center Web Site

Image 22

Motorola MVME2600 manual MVME2603/2604 Base Board Block Diagram

Contents

Installation and Use Page Safety Summary Flammability CE Notice European Community Limited and Restricted Rights Legend Contents Chapter Connector Pin Assignments Appendix a Appendix D Related Documentation Page List of Figures Page List of Tables Xvi About This Manual Model Number Description Overview of Contents Summary of Changes Comments and Suggestions Conventions Used in This Manual Bold Hardware Preparation and Installation Introduction MVME2603/2604 Base Board Block Diagram Equipment Required Overview of Startup ProcedureStartup Overview Connector Pin Assignments What you need to do Refer to Hardware Configuration Unpacking Instructions MVME2603/2604 Base Board Preparation Cache Mode Control J3 Flash Bank Selection J10 Serial Port 4 Receive Clock Configuration J16 MVME2603/2604 Switches, Headers, Connectors, Fuses, LEDs Serial Port 4 Transmit Clock Configuration J17 Serial Port 4 Transmit Clock Receiver Buffer Control J20 Serial Port 3 Transmit Clock Configuration J18 System Controller Selection J22 MVME712M Transition Module Preparation Remote Status and Control MVME712M Transition Module Preparation OnnectorCLocationsFigure 1-3. MVME712Mand Header Literature1-16Computer GroupCenter Serial Port Board Panel Connector Jumper Header Serial Ports 1-4 DCE/DTE ConfigurationSerial Port 4 Clock Configuration MVME712M Port/Jumper Correspondence MVME712M Serial Port 1 DCE/DTE Configuration MVME712M Serial Port 2 DCE/DTE Configuration MVME712M Serial Port 3 DCE Configuration MVME712M Serial Port 3 DTE Configuration MVME712M Serial Port 4 DCE Configuration 10. MVME712M Serial Port 4 DTE Configuration 11. MVME712M P2 Adapter Component Placement P2 Adapter Preparation MVME761 Transition Module Preparation 12. MVME761 Connector and Header Locations Serial Ports 1 Configuration of Serial Ports 3Port Connector Header J12 Synchronous Board J2J2 13. MVME761 Serial Ports 1 and 2 DCE Only 14. MVME761 Serial Ports 3 and 4 DCE Configuration 15. MVME761 Serial Ports 3 and 4 DTE Configuration P2 Adapter Preparation Three-Row 16. MVME761 P2 Adapter Three-Row Component Placement P2 Adapter Preparation Five-Row 17. MVME761 P2 Adapter Five-Row Component Placement Hardware Installation RAM200 Memory Mezzanine Installation Hardware Preparation and Installation PMC Module Installation 18. RAM200 Placement on MVME2603/2604 Hardware Preparation and Installation 19. PMC Module Placement on MVME2603/2604 PMC Carrier Board Installation 20. PMC Carrier Board Placement on MVME2603/2604 MVME2603/2604 VME Module Installation Hardware Installation MVME712M Transition Module Installation Hardware Installation Hardware Preparation and Installation 21. MVME712M/MVME2603/2604 Cable Connections MVME761 Transition Module Installation 22. MVME761/MVME2603/2604 Cable Connections System Considerations MVME2603/2604 VME Module Hardware Preparation and Installation System Considerations Page Applying Power Operating Instructions PPCBug System Startup Reset Switch S2 Abort Switch S1Applying Power Front Panel Indicators DS1 DS6 Memory Maps Processor Memory Map Processor Default View of the Memory Map Default Processor Memory MapProcessor Address Size Definition Start End PCI Local Bus Memory Map VMEbus Memory Map Programming Considerations VMEbus Master Mapping PCI Arbitration Assignments PCI ArbitrationPCI Bus Request PCI Masters Interrupt Handling Programming Considerations MVME2603/MVME2604 Interrupt Architecture IBC DMA Channel Assignments Sources of ResetDMA Channels Controller DMA Assignment Priority Label Classes of Reset and Effectiveness Asic Processor/Memory Domain Endian IssuesPCI Domain PCI and Scsi VMEbus Domain Feature Description FeaturesMVME2603/2604 Features ECC Dram VME I/O Scsi I/O General Description Block Diagram MVME2603/2604 Block Diagram Scsi Interface Scsi Termination Ethernet Interface PCI Mezzanine Interface PMC ConnectorsSignaling Voltage Mezzanine Type VMEbus Interface ISA Super I/O Device Isasio Asynchronous Serial Ports Parallel Port Disk Drive Controller PCI-ISA Bridge PIB ControllerKeyboard and Mouse Interface Real-Time Clock/NVRAM/Timer Function Programmable Timers Interval Timers Bit Timers Serial Communications Interface Z8536 CIO Device Base Module Feature RegisterBase Module Feature Register Offset $0802 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 P2 Signal Multiplexing P2 Multiplexing Sequence DCD1 RLB4 DCD4 Idreq ∗ TM4/MID2 DTR1 RI4 DTR2 RI1DSR1 RI2 Front Panel Indicators DS1 DS6 Fuse Assignments Polyswitches Resettable FusesPower Fuse Voltage Speaker Control PM603/604 Processor RAM200 Memory Module Flash Memory MVME712M Transition Module MVME761 Transition Module Serial Interface Modules SIM Type Identification Model Module Number TypePage Connector Pin Assignments MVME2603/2604 Connectors Connector Pin Assignments LED Mezzanine Connector J1 Common ConnectorsLED Mezzanine Connector PA0 PA1 Debug Connector J2Debug Connector GND PDPAR4 PDPAR5 PDPAR0 PDPAR1PDPAR2 PDPAR3 PDPAR6 PDPAR7 TT2 TSIZ2 TT0 TSIZ0TT1 TSIZ1 TT3 TC0 Floppy/LED Connector J4 Floppy/LED Connector PCI Expansion Connector J5 PCI Expansion Connector GND Trdy ∗ Irdy ∗ Trst ∗ PMC2P ∗ PMC2GNT ∗ PMC2REQ ∗Lock ∗ Sdone Devsel ∗ PAR PAR64 Keyboard Connector Keyboard and Mouse Connectors J6, J8Mouse Connector Dram Mezzanine Connector Dram Mezzanine Connector J7Aras ∗ Acas ∗ RDL58 RDL59 RDL6 RDL7 RDL8 RDL9 RDL10 RDL11 RDL12RDL56 RDL57 RDL60 RDL61 CDL6 CDL7 CDL2 CDL3CDL4 CDL5 RDU0 RDU1 PCI Mezzanine Card Connector PCI Mezzanine Card ConnectorsJ11 J12 J13 J14 PMCIO16 PMCIO17 GND PMCIO12 PMCIO13PMCIO14 PMCIO15 GND PMCIO18 PMCIO19 VMEbus Connector P1 VMEbus Connector P1Row Z Row a Row B Row C Row D 10. VMEbus Connector P2 MVME712M I/O Mode VMEbus Connector P2MVME712M-Compatible Versions SDBP0 PMCIO4 GNDPMCIO6 GND PMCIO8 GND GND DBP ∗ Scsi Connector11. Scsi Connector MVME712M Termpwr GND ATN ∗ BSY ∗ ACK ∗ RST ∗ MSG ∗ SEL ∗ REQ ∗ Serial Ports 12. Serial Connections-MVME712M Ports Prstb ∗ GND PRD0 PRD1 PRD2 PRD3 PRD4 PRD5 PRD6 PRD7 Parallel Connector13. Parallel I/O Connector MVME712M GND Prbsy Prpe Prsel Inprime ∗ Ethernet AUI Connector 14. Ethernet AUI Connector MVME712M MVME761-Compatible Versions 15. VMEbus Connector P2 MVME761 I/O ModePMCIO16 16. Serial Connections-Ports 1 and 2 MVME761 Serial Ports 3 17. Serial Connections-Ports 3 and 4 MVME761 Prbsy GND Prsel 18. Parallel I/O Connector MVME761GND Prpe PRD0 PRD1 PRD2 PRD3 PRD4 PRD5 PRD6 PRD7 Ethernet 10BaseT/100BaseTX Connector 19. Ethernet 10BaseT/100BaseTX Connector MVME761Page PPCBug Overview Memory Requirements PPCBug Implementation Using the Debugger Debugger Commands Debugger CommandsCommand Description Fork GevbootENV Forkwr MAW PbootReset MD, MDS Srom RUNSET SYM Diagnostic Test Groups Diagnostic TestsTest Set Description Applicability Cnfg and ENV Commands Cnfg Configure Board Information Block Configuring the PPCBug Parameters ENV Set Environment Remote Start Method Switch G/M/B/N = B? Wide Scsi 16-bit bus Narrow Scsi 8-bit bus. Default Nvram Bootlist GEV.fw-boot-path Boot Enable Y/N = N? Default = $00 Auto Boot Abort Delay = 7? ROM Boot Direct Ending Address = FFFFFFFC? Default Starting Address is $00000000 ROM Next Access Length 0 15 = 0? Configuring the VMEbus Interface PCI Slave Image 0 Bound Address Register = 00000000? PCI Slave Image 3 Control = C0400000? VMEbus Slave Image 1 Base Address Register = 00000000? VMEbus Slave Image 3 Translation Offset = 00000000? Table A-1. MVME2603/2604 Specifications SpecificationsCharacteristics Specifications Cooling Requirements FCC Compliance Page Asynchronous Serial Ports Synchronous Serial Ports EIA-232-D Connections Table B-1. EIA-232-D Interconnect Signals Pin Signal Signal Name and Description Number Mnemonic BSY Table B-2. EIA-232-D Interface Transmitter Characteristics Interface CharacteristicsTable B-3. EIA-232-D Interface Receiver Characteristics Table B-4. MVME761 EIA-530 Interconnect Signals EIA-530 Connections EIA-530 Connections Table B-5. EIA-530 Interface Transmitter Characteristics Table B-6. EIA-530 Interface Receiver Characteristics Proper GroundingPage CTroubleshooting CPU Boards Solving Startup Problems Table C-1. Troubleshooting MVME2603/2604 Boards Troubleshooting CPU Boards Solving Startup Problems Introduction Troubleshooting Procedure Complete Motorola Computer Group Documents Document Title Publication Number Manufacturers’ Documents Document Title and Source Publication Number MPCFPE/AD MPC2604GA CA91C042 ANSI/IEEE Related SpecificationsIEC 821 BUS MPR-PPC-RPU-02 Isbn Member countries TIA/EIA-232Page Index Dram PCI bus 2-4,2-7,3-3,3-7,3-11,3-17 Romnal Scsi 10,2-14,2-16,3-8,3-17 uppercase