Motorola MVME2600 manual Memory Maps, Processor Memory Map

Memory Maps

Memory Maps

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There are three points of view for memory maps:

❏The mapping of all resources as viewed by the processor (MPU bus memory map)

❏The mapping of onboard resources as viewed by PCI local bus masters (PCI bus memory map)

❏The mapping of onboard resources as viewed by VMEbus masters (VMEbus memory map)

The following sections give a general description of the MVME2603/2604 memory organization from the above three points of view. Detailed memory maps can be found in the MVME2600 Series Single Board Computer Programmer’s Reference Guide, listed in Appendix D, Related Documentation.

Processor Memory Map

The processor memory map configuration is under the control of the Raven bridge controller ASIC and the Falcon memory controller chip set. The Raven and Falcon devices adjust system mapping to suit a given application via programmable map decoder registers. At system power-up or reset, a default processor memory map takes over.

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