Motorola MVME2600 manual Real-Time Clock/NVRAM/Timer Function

Block Diagram

The PIB controller provides the following functions:

❏PCI bus arbitration for:

–ISA (Industry Standard Architecture) bus DMA

–The PHB (PCI Host Bridge) MPU/local bus interface function, implemented by the Raven ASIC

–All on-board PCI devices

–The PMC (PCI Mezzanine Card) slot

❏ISA (Industry Standard Architecture) bus arbitration for DMA devices

❏ISA interrupt mapping for four PCI interrupts

❏Interrupt controller functionality to support 14 ISA interrupts

❏Edge/level control for ISA interrupts

❏Seven independently programmable DMA channels

❏One 16-bit timer

❏Three interval counters/timers

Accesses to the configuration space for the PIB (PCI/ISA Bridge) controller are performed by way of the CONADD and CONDAT (Configuration Address and Data) registers in the Raven bridge controller ASIC. The registers are located at offsets $CF8 and $CFC, respectively, from the PCI I/O base address.

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Real-Time Clock/NVRAM/Timer Function

The MVME2603/2604 employs an SGS-Thomson surface-mount M48T59/T559 RAM and clock chip to provide 8KB of non-volatile static RAM, a real-time clock, and a watchdog timer function. This chip supplies a clock, oscillator, crystal, power failure detection, memory write protection, 8KB of NVRAM, and a battery in a package consisting of two parts:

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