AWARD® BIOS Setup
Advanced Chipset Features
CMOS Setup Utility - Copyright (C)
Advanced Chipset Features
Configure DRAM Timing | [By SPD] | Item Help | |
| CAS# Latency | [1.5] |
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| Precharge Delay | [7] |
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| RAS# to CAS# Delay | [3] | Menu Level 8 |
| RAS# Precharge | [3] |
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DRAM Data Integrity Mode |
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Memory Hole At | [Disabled] |
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Delayed Transaction | [Enabled] |
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AGP Aperture Size (MB) | [64] |
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↑↓→← | :Move Enter:Select | ESC:Exit F1:General Help | |
| F5:Previous Values | ||
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Note: Change these settings only if you are familiar with the chipset.
Configure SDRAM Timing
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect) EEPROM on the DRAM module. Setting to By SPD enables CAS# Latency, RAS# Precharge, RAS# to CAS# Delay and RAS# Precharge automatically to be determined by BIOS based on the configurations on the SPD. Selecting By Manual allows users to configure these fields manually.
CAS# Latency
This controls the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. Settings: 1.5, 2, 2.5 and 3 (clocks). 1.5 (clocks) increases the system performance the most while 3 (clocks) provides the most stable performance.
Precharge Delay
The field specifies the idle cycles before precharging an idle bank. Settings: 7, 6 and 5 (clocks).
