Premio Computer Aries/Centella manual RAS# to CAS# Delay, Precharge Delay, DRAMIntegrityMode

AMI® BIOS Setup

allowed to precharge. If insufficient time is allowed for the RAS to accumu- late its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. Available settings: 3 Clocks and 2 Clocks.

RAS# to CAS# Delay

This field allows you to set the number of cycles for a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read from or refreshed. Fast speed offers faster performance while slow speed offers more stable performance. Settings: 3 Clocks and 2 Clocks.

Precharge Delay

The field specifies the idle cycles before precharging an idle bank. Settings: 7 Clocks, 6 Clocks and 5 Clocks.

DRAMIntegrityMode

Select ECC (Error-Correcting Code) or Non-ECCaccording to the type of installed DRAM.

AGP Aperture Size

The field selects the size of the Accelerated Graphics Port (AGP) aperture. Aperture is a portion of the PCI memory address range dedicated for graphics memory address space. Host cycles that hit the aperture range are forwarded to the AGP without any translation. Settings: 4MB, 8MB, 16MB, 32MB, 64MB, 128MB and 256MB.

Delayed Transaction

The chipset has an embedded 32-bit posted write buffer to support delayed transactions cycles so that transactions to and from the ISA bus are buff- ered and PCI bus can perform other transactions while the ISA transaction is underway. Select Enabled to support compliance with PCI specification version 2.1. Settings: Enabled and Disabled.

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