Premio Computer Aries/Centella manual RAS# to CAS# Delay, RAS# Precharge, DRAMDataIntegrityMode

Chapter 3

RAS# to CAS# Delay

This field allows you to set the number of cycles for a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read from or refreshed. Fast speed offers faster performance while slow speed offers more stable performance. Settings: 3 and 2 (clocks).

RAS# Precharge

This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumu- late its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. Available settings: 3 and 2 (clocks).

DRAMDataIntegrityMode

Select ECC (Error-Correcting Code) or Non-ECCaccording to the type of installed DRAM.

Memory Hole At 15M-16M

In order to improve performance, certain space in memory can be reserved for ISA peripherals. This memory must be mapped into the memory space below 16MB. When this area is reserved, it cannot be cached. Settings:

Enabled and Disabled.

Delayed Transaction

The chipset has an embedded 32-bit posted write buffer to support delayed transactions cycles so that transactions to and from the ISA bus are buff- ered and PCI bus can perform other transactions while the ISA transaction is underway. Select Enabled to support compliance with PCI specification version 2.1. Settings: Enabled and Disabled.

AGP Aperture Size (MB)

The item is used to select the size of Accelerated Graphics Port (AGP) aperture. Aperture is a portion of PCI memory address range dedicated for graphics memory address space. Host cycles that hit the aperture range are forwarded to AGP without any translation. Settings: 4, 8, 16, 32, 64, 128 and 256.

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