Programming the Board | 36 |
Overview | 36 |
Register tables | 36 |
Programming examples | 36 |
Error handling | 36 |
Initialization | 37 |
Starting the automatic initialization routine | 37 |
PCI Register | 37 |
Hardware version | 38 |
Date of production | 38 |
Serial number | 38 |
Maximum possible sample rate | 38 |
Installed memory | 38 |
Installed features and options | 38 |
Used interrupt line | 39 |
Used type of driver | 39 |
Powerdown and reset | 40 |
Analog Inputs | 41 |
Channel Selection | 41 |
Important note on channels selection | 41 |
Channel rerouting | 42 |
Setting up the inputs | 43 |
Input ranges | 43 |
Input offset | 44 |
Overrange bit | 45 |
Input termination | 45 |
Automatical adjustment of the offset settings | 45 |
Standard acquisition modes | 47 |
General Information | 47 |
Programming | 47 |
Memory, Pre- and Posttrigger | 47 |
Starting without interrupt (classic mode) | 48 |
Starting with interrupt driven mode | 49 |
Data organization | 50 |
Sample format | 50 |
Reading out the data with SpcGetData | 51 |
FIFO Mode | 53 |
Overview | 53 |
General Information | 53 |
Background FIFO Read | 53 |
Speed Limitations | 53 |
Programming | 54 |
Software Buffers | 54 |
Buffer processing | 55 |
FIFO mode | 56 |
Example FIFO acquisition mode | 56 |
Data organization | 56 |
Sample format | 57 |
Clock generation | 58 |
Overview | 58 |
Internally generated sample rate | 58 |
Standard internal sample rate | 58 |
Using plain quartz without PLL | 59 |
External clocking | 60 |
Direct external clock | 60 |
External clock with divider | 61 |
Trigger modes and appendant registers | 62 |
General Description | 62 |
Software trigger | 62 |
External TTL trigger | 62 |
Edge triggers | 63 |
Pulsewidth triggers | 64 |
Channel Trigger | 66 |
Overview of the channel trigger registers | 66 |
Triggerlevel | 67 |
Detailed description of the channel trigger modes | 69 |
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